Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
1999-11-24
2004-10-12
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
C375S365000, C375S366000, C375S377000
Reexamination Certificate
active
06804316
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to network communications and, more particularly, to identifying a framing pattern in a stream of data.
BACKGROUND OF THE INVENTION
In data communications systems, data is typically transmitted as a series of frames. Each frame often begins with a framing pattern followed by the data information being transmitted. The receiving device detects the framing pattern to establish synchronization with the transmitting device. The receiving device is then able to process the data being transmitted.
For example, in a synchronous optical network (SONET) operating at a Synchronous Transport Signal level 1 (STS-1), each STS-1 frame consists of a serial bit stream of 810 bytes. The framing pattern for an STS-1 signal is dedicated to the first two bytes, A
1
and A
2
, of each STS-1 frame. The pattern for bytes A
1
and A
2
is F
628
Hex (1111011000101000) where A
1
equals F
6
Hex (11110110) and A
2
equals 28 Hex (00101000). Higher rates (STS-N) in SONET are achieved by byte interleave multiplexing an N number of STS-1 frames. The framing pattern for an STS-3 frame in an Optical Carrier level 3 (OC-3) system is A
1
A
1
A
1
A
2
A
2
A
2
. Similarly, the framing pattern for an STS-192 frame in an OC-192 system is 192 A
1
bytes followed by 192 A
2
bytes.
A frame recovery circuit in the receiving apparatus searches the incoming frame for the framing pattern. After recognizing the framing pattern, the frame recovery circuit operates to provide a synchronization indication and resynchronize the receiver to the incoming data stream, in a minimum amount of time.
One drawback with conventional SONET framing recovery systems is that the frame recovery time, i.e., the time it takes the receiving device to identify the framing pattern, is too long. As network speeds achieve 10 Gb/s and higher, these high recovery times become unacceptable and result in the loss of information. Prior art systems concerned with decreasing the frame recovery time, however, often leave the system vulnerable to bit error problems or datagram attacks from a hacker, thereby causing a false synchronization indication. A bit error occurs when the frame recovery circuit misidentifies a sequence of data as equivalent to the framing pattern. A datagram attack, in contrast, is a sequence of data which, when encoded with a scrambling sequence, contains the framing pattern. In either situation, the system provides a false synchronization indication.
Another system that attempts to reduce the recovery time converts the serial bit stream into parallel units of data. However, the recovery circuit examines a 15-bit wide word to identify and determine the phase of each full eight-bit A
1
and A
2
pattern. For systems operating at high speeds, examining and looking for the framing pattern in this manner is too time consuming, resulting in the loss of information. Additionally, in high-speed systems, it would not be uncommon to find a random string of data equal to the framing pattern. Therefore, the prior art system is also susceptible to false synchronization indications.
Therefore, a need exists for a frame recovery system which reduces the frame recovery time and is less vulnerable to false synchronization indications.
SUMMARY OF THE INVENTION
Systems and methods consistent with the present invention address this need by performing frame pattern recognition quickly while reducing the susceptibility of the network to malicious attacks or to random sequences of bit streams.
In accordance with the purpose of the invention as embodied and broadly described herein, a system consistent with the present invention includes a data scanner and a frame detector. The data scanner examines parallel bytes of data and detects portions of a framing pattern in the parallel bytes. The data scanner also identifies the phase of the framing pattern and outputs alignment information and phase information when a framing pattern has been detected. The frame detector receives the alignment information and phase information and determines whether framing patterns having the same phase relationship have been detected within a predetermined number of frames.
REFERENCES:
patent: 5081654 (1992-01-01), Stephenson, Jr. et al.
patent: 5113417 (1992-05-01), McNesby
patent: 5400369 (1995-03-01), Ikemura
patent: 5570370 (1996-10-01), Lin
patent: 5592518 (1997-01-01), Davis et al.
patent: 6246736 (2001-06-01), Coady
patent: 6298387 (2001-10-01), Prasad et al.
Chin Stephen
Finnegan Henderson et al
Muñoz Guillermo
Suchyta, Esq. Leonard C.
Verizon Corporate Services Group Inc.
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