Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-04-24
2003-04-22
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S019000, C710S020000, C710S029000, C710S053000, C710S056000, C710S061000, C709S241000, C709S248000, C709S241000
Reexamination Certificate
active
06553438
ABSTRACT:
BACKGROUND
1. Field
This invention relates to message buffers for transferring information over a channel-based switched fabric, and more specifically to message resource pools of buffers with asynchronous and synchronous modes of operation.
2. Background
Transfers of information, e.g., data and/or messages, over a channel-based switched fabric usually occur between a host and a target. The host may contain one or more processing units, applications, device drivers, etc. that initiate the transfer, that may be a read or write, between the host and the target. A target may be an I/O controller that may have one or more I/O devices attached to it. Data and/or message transfers may occur between a host and a target by passing control of buffers, that contain the data or messages, between the host and the target. For example, a host may desire to write data to an I/O controller. The host may then store the data it desires to transfer into a series of buffers. The host may then transfer control of these buffers to the I/O controller. The I/O controller then may move the data contained in these buffers at a time convenient to the I/O controller. Similarly, if a host desires to read data or messages from an I/O controller or device attached to an I/O controller, the host may pass control of buffers to the I/O controller. The I/O controller then may write the data from the I/O device to the buffer contained in the host at a time convenient for the I/O controller. Upon completion of a transfer, control of the buffers may then be passed back to the owner (e.g., host) of the buffer.
Host memory regions that are the source or target of data/message passing operations are locked in physical memory from the time that a message passing operation is initiated until the time it completes. This locking insures that the page in memory is physically present when the host or target attempts to read from or write to it, and that the logical to physical mapping of pages in the memory do not change during the operation. Host memory regions that are used to transfer messages and/or data may be required to be registered with a host unit management function. The host unit management function may pass information regarding memory registration to other parts of the host unit that may need it (e.g., switched fabric hardware interface), and may be implemented in hardware, software, or a combination thereof. The unit management function may provide other administrative/management activities or functions on the host unit. A similar unit management function may exist on the target side of the switched fabric. Registration may allow the use of virtual addresses and may also provide a mechanism for protection.
Regions of virtual memory that are used as buffers for I/O operations and that occupy more than a single page may not be physically contiguous. By registering these memory regions, message passing descriptors can refer to them as a single entity rather than a scatter-gather list of physical pages. A scatter-gather list may contain a list of addresses pointing to areas in memory that are to be accessed sequentially. These areas maybe non-contiguous and scattered throughout a memory space. The data is transferred as though all the data is being accessed from one continuous memory. Memory registration gives a host the information it needs to translate virtual addresses to physical addresses on the fly as message passing operations are performed.
Memory registration also provides the ability to protect regions of memory from being accessed and/or modified by another. Devices attached via a PCI bus may be able to read and write any host memory location. As I/O units migrate further away from the host CPU/memory complex, additional protection may be warranted to protect host memory from malfunctioning or malicious devices.
REFERENCES:
patent: 5982780 (1999-11-01), Bohm et al.
patent: 6125399 (2000-09-01), Hamilton
patent: 6233623 (2001-05-01), Jeffords et al.
patent: 2001/0014918 (2001-08-01), Harter et al.
Coffman Jerrie L.
Hefty Mark S.
Tillier Fabian S.
Antonelli Terry Stout & Kraus LLP
Casiano Angel L
Gaffin Jeffrey
Intel Corporation
LandOfFree
Methods and system for message resource pool with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and system for message resource pool with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and system for message resource pool with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3018626