Electrical computers and digital data processing systems: input/ – Interrupt processing – Processor status
Reexamination Certificate
2011-03-01
2011-03-01
Knoll, Clifford H (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Processor status
C710S261000
Reexamination Certificate
active
07899966
ABSTRACT:
A method for distributing interrupt load to processors in a multiprocessor system. The method includes executing current transactions with multiple processors (104, 106, 108) where each transaction is associated with one of the processors, generating an interrupt request, estimating a transaction completion time for each processor and directing the interrupt request (102) to the processor having the least estimated transaction completion time. Estimating a transaction completion time occurs periodically so that information pertaining to transaction times is stored and continually updated. According to one aspect of the invention, the step of estimating a transaction completion time for each processor occurs when the interrupt request is generated. According to another aspect of the invention, the step of communicating the interrupt request includes communicating the interrupt request to an intermediary processor prior to estimating the transaction completion time.
REFERENCES:
patent: 6237058 (2001-05-01), Nakagawa
patent: 6606676 (2003-08-01), Deshpande et al.
patent: 6804790 (2004-10-01), Rhee et al.
patent: 2002/0152374 (2002-10-01), Mayfield
patent: 2004/0103251 (2004-05-01), Alsup
Knoll Clifford H
NXP B.V.
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