Methods and system for analysis and management of parametric...

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Yield

Reexamination Certificate

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C716S051000, C716S054000

Reexamination Certificate

active

08042070

ABSTRACT:
Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

REFERENCES:
patent: 2002/0193892 (2002-12-01), Bertsch et al.
patent: 2008/0005707 (2008-01-01), Papanikolaou et al.
patent: 2008/0231307 (2008-09-01), Bickford et al.
patent: 2009/0031271 (2009-01-01), White et al.
Cox et al.; “Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits”; Feb. 1985; IEEE Transactions on Electron Devices; pp. 471-478.
Rao et al; “Parametric Yield Estimation Considering Leakage Variability”; 2004; Design Automation Conference, 41st Conference; pp. 442-447.
Kim et al.; “Dynamic Vth Scaling Scheme for Active Leakage Power Reduction”; 2002; Department of Electrical and Computer Engineering at Purdue University; pp. 1-5.

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