Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-04-04
1998-06-02
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711114, 711142, 711143, 711162, 39518204, 39518205, G06F 1208, G06F 1316, G06F 1114
Patent
active
057617058
ABSTRACT:
Methods and associated apparatus operable in a RAID subsystem having redundant disk array controllers to assure dual, redundant cache consistency while permitting operation of the RAID subsystem in response to host computer I/O requests. The methods and apparatus of the present invention provide for a process of initializing the redundant disk array controllers in response to a power-on reset cycle (or other similar reset cycles). The first controller partially initializes for processing of host requests then awaits the partial initialization of the second controller. After a brief timeout awaiting the second controller, or in response to an erroneous initialization of the second controller, the first controller configures itself to perform host computer I/O requests in a write-through mode (bypassing cache operations) until the second controller eventually initializes. Once both controller are initialized, the redundant caches are synchronized. Finally, the initialized controllers having synchronized the redundant caches begin normal, mirrored, redundant operation. Until such time as the redundant caches are synchronized, the first controller continues operations in response to host computer I/O requests but with the degraded performance associated with the cache write-through mode.
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David A. Patterson, Garth Gibson and Randy H. Katz; A Case for Redundant Arrays of Inexpensive Disks(RAID); Dec. 1987; Report No. UCB/CSD 87/391.
DeKoning Rodney A.
Humlicek Donald R.
Johnson Max L.
Bailey Wayne P.
Bragdon Reginald G.
Chan Eddie P.
Fishman Daniel L.
Symbios, Inc.
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