Methods and semiconductor structures for latch-up...

Details Methods and semiconductor structures for latch-up... Methods and semiconductor structures for latch-up...

2006-01-26

2009-02-17

Le, Thao X (Department: 2892)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including isolation structure

C438S430000, C257S372000

Reexamination Certificate

active

07491618

ABSTRACT:
Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

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