Methods and semiconductor devices with wiring layer fill...

Details Methods and semiconductor devices with wiring layer fill... Methods and semiconductor devices with wiring layer fill...

2003-03-13

2004-02-17

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S774000, C257S775000, C257S762000

Reexamination Certificate

active

06693357

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to fabrication methods and devices employing wiring layer conductive fill structures to facilitate uniform planarization in manufacturing semiconductor devices.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor products such as integrated circuits, individual electrical devices are formed on or in a semiconductor body, and are thereafter interconnected to form electrical circuits. Interconnection of these devices within an integrated circuit (sometimes referred to as metalization or interconnect processing) is typically accomplished by forming a multi-level interconnect network structure in layers formed over the electrical devices, by which the electrical components are interconnected to create the desired circuits. Individual wiring layers within the multi-level interconnect network are formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching openings or cavities such as vias and/or trenches. Conductive material is then deposited into the openings to form inter-layer contacts and wiring traces. The wafer is then planarized to separate the conductive material in the individual cavities, thereby creating one level or interconnect layer. Dielectric or insulating material is then deposited over this layer and the process may be repeated any number of times to construct additional wiring levels formed within the additional dielectric layers with conductive vias therebetween to form the multi-level interconnect network.
As device densities and operational speeds continue to increase, reduction of the delay times in integrated circuits is desired. These delays are sometimes related to the resistance of interconnect metal lines through the multi-layer interconnect networks as well as to the capacitance between adjacent metal lines. In order to reduce the resistivity of the interconnect metal lines formed in metal layers or structures, recent interconnect processes have employed copper instead of aluminum. Interconnect layers using copper are commonly fabricated using single and dual damascene interconnect processes or techniques in which cavities, such as vias and trenches, are formed (etched) in a dielectric insulating layer. Copper is deposited into the cavities and over the insulating layer, typically using electro-chemical deposition (ECD) techniques preceded by formation of appropriate diffusion barrier and copper seed layers. Once the copper is deposited to fill the cavities, planarization using a chemical mechanical polishing (CMP) or other process is performed, leaving a copper wiring pattern including the desired interconnect metal lines inlaid within the dielectric layer trench and via cavities. In a single damascene process, copper trench patterns or vias are created which connect to existing interconnect structures thereunder, whereas in a dual damascene process, both vias and the trenches are filled at the same time using a single copper deposition and are then planarized using a single CMP planarization operation.
Depending upon the particular circuits and components fabricated in a wafer, the conductive interconnect wiring structures employed for interconnecting components are often of varying dimensions in a given integrated circuit. For instance, lines carrying low amounts of current may be made relatively narrow, whereas power connections and other routing structures required to conduct larger amounts of current need to be made wider (e.g., larger cross sectional area) so as to reduce line resistance and thereby to reduce power loss through heating. Interconnect wiring structure dimensions may also be tailored with an eye toward reducing RC time delays in high speed circuitry. In typical damascene interconnect structures, the depth of trenches filled with copper for interconnection of electrical devices is uniform across the device in any given layer. Consequently, designers vary the trench widths for different routed signals in each metalization layer to control the resistivity of the resulting wiring structure, where wider trenches are used for higher current interconnections.
At the same time, certain signals may need to be separated from other signals by minimum spacing distances, where such design considerations affect the wiring density, and hence the number of interconnect levels required to interconnect a given circuit. In this regard, manufacturing costs increase as more routing or interconnect layers are added. As device densities and routing densities continue to be increased, wiring structure widths have become smaller, wherein narrow wiring structures are formed using trenches and vias having fairly large aspect ratios (e.g., the ratio of the cavity height to the cavity width), and wider wiring structures are formed using lower aspect ratio cavities. The resulting wiring structures after planarization have corresponding aspect ratios, where the height may be reduced somewhat by the planarization process.
Ideally, the deposition of copper is uniform during interconnect layer fabrication, and the subsequent planarization step leaves the wafer with a smooth planar surface. However, conventional copper deposition processing techniques often result in surface topology variations across a wafer surface prior to planarization. CMP planarization processing in the presence of such topology is non-uniform, resulting in more material being removed from certain areas than from others (sometimes referred to as dishing). As a result, non-uniform surface topology remains following the planarization process. Subsequent processing steps, such as patterning overlying insulating layers to form further interconnect layers in the presence of such topology variations may be adversely affected by such non-uniform surface topology. Thus, there is a need for improved interconnect processing techniques by which topology variation can be mitigated or reduced in the manufacture of semiconductor devices.
SUMMARY OF THE INVENTION
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. The invention relates to semiconductor devices and manufacturing methods therefor, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing.
In accordance with one aspect of the invention, conductive dummy fill structures of varying sizes are employed in fill regions between wiring regions. This may be employed to advantageously provide more uniform conductive material deposition, resulting in improved planarization uniformity. In one example, smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures, wherein the fill structures may be patterns of varying pattern size. This provides a gradual transition between overfilled and conformally filled wiring regions and thus better uniformity in deposited conductive material thickness, compared with layouts having no dummy fill features, or dummy metal fill structures of a single size and shape. Accordingly, better planarization uniformity may be achieved, for example, having less overpolish and underpolish during CMP processing. This aspect of the invention may be employed during device layout to tailor dummy metal fill for individual metal layer mask designs.
Another aspect of the invention provides conductive fill structures with varying amounts of openings. In one example, the fill structures are conductive areas formed into patterns, wherein one or more of the conductive areas include slot shaped openings comprising insula

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