Methods and media for forming a bound network

Details Methods and media for forming a bound network Methods and media for forming a bound network

2007-02-01

2010-11-23

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07840915

ABSTRACT:
Methods and media for forming a bound network are provided. In some embodiments, methods for forming a bound network include: decomposing an asynchronous input network to form a network of base functions, wherein the network of base functions includes simple base functions that include two-input threshold OR functions and two-input threshold AND functions with hysteresis, and complex base functions generated during the decomposing; partitioning the network of base functions into at least one subject graph, each portion of the at least one subject graph having a function; determining matches between the at least one subject graph and one or more pattern graphs; and selecting at least one of the one or more pattern graphs to be used in the bound network for the function of each of different portions of the at least one subject graph.

REFERENCES:
patent: 6020754 (2000-02-01), Sobelman et al.
patent: 6031390 (2000-02-01), Fant et al.
patent: 6334205 (2001-12-01), Iyer et al.
patent: 6557144 (2003-04-01), Lu et al.
patent: 2008/0163152 (2008-07-01), Kheterpal et al.
Beerel, P. A., “CAD Tools for the Synthesis, Verification, and Testability of Robust Asynchronous Circuits,” PhD thesis, Stanford University, 1994.
Beerel et al., “Optimizing average-case delay in technology mapping of burst-mode circuits,” Int. Symp. Asynchronous Circuits and Systems, 1996, pp. 244-259.
Brej, C. F., “Early Output Logic and Anti-Tokens,” PhD thesis, University of Manchester, 2005.
Burns, S. M., “General conditions for the decomposition of state holding elements,” In Proc. Int. Symp. Asynchronous Circuits and System, 1996, pp. 48-57.
Chaudhary et al., “Computing the area versus delay tradeoff curves in technology mapping,” IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., Dec. 1995, 1):1480-1489.
Chelcea et al., “Resynthesis and peephole transformations for the optimization of large-scale asynchronous system,” In Proc. ACM/IEEE Des. Autom. Conf., 2002, pp. 405-410.
Constantinescu, C., “Trends and challenges in VLSI circuit reliability,” IEEE Micro, 2003, 23(4):14-19.
Cortadella, J., “Decomposition and technology mapping of speed-independent circuits using Boolean relations,” IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., 1999, 18(9):1221-1236.
Cortadella, J et al. “Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers,” IEICE Trans. Information and Systems, 1997, E80-D:315-325.
Cortadella, J. et al. “Coping with the variability of combinational logic delays,” In Proc. Int. Conf Computer Design, 2004, pp. 505-508.
David, I. et al. “An efficient implementation of boolean functions as self-timed circuits,” IEEE Trans. Comput., 1992, 41(1):2-11.
Folco, B. et al. “Technology mapping for area optimized quasi delay insensitive circuits,” In Proc. IFIP Conf. Very Large Scale Integration Systems, 2005.
Ho, Q. T. et al. “Implementing asynchronous circuits on LUT based FPGAs,” In Proc. Int. Symp. Field Programmable Logic and Applications, 2002, pp. 36-46.
James, K. W. et al. “Average-case optimized transistor-level technology mapping of extended burst-mode circuits,” In proc. Int. Symp. Asynchronous Circuits and Systems, 1998, pp. 70-79.
Jeong C. et al. “Optimal technology mapping and cell merger for asynchronous threshold circuits,” In Proc. Int. Symp. Asynchronous Circuits and Systems, 2006, pp. 128-137.
Jeong et al. “Optimization of robust asynchronous circuits by local input completeness relaxation,” In Asia and South Pacific Des. Autom. Conf., 2007.
Keutzer, K. “DAGON: Technology binding and local optimization by DAG matching,” In Proc. Des. Autom. Conf., 1987, pp. 341-347.
Kondratyev, A. et al. “Logic decomposition of speed-independent circuits,” Proc. IEEE, 1999, 87(2):347-362.
Kondratyev, A. et al. “Design of asynchronous circuits using synchronous CAD tools,” IEEE Design & Test of Computers, 2002, 19(4):107-117.
Kondratyev, A. et al. “Checking delay-insensitivity: 104gates and beyond,” In Proc. Int. Symp. Asynchronous Circuits and Systems, 2002, pp. 149-157.
Kudva, P. et al. “Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes,” In Proc. ACM/IEEE Des. Autom. Conf., 1996, pp. 77-82.
Kukimoto, Y. et al. “Delay-optimal technology mapping by DAG covering, ” In Proc. ACM/IEEE Des. Autom. Conf., 1998, pp. 348-351.
Ligthart, M. et al. “Asynchronous design using commercial HDL synthesis tools,” In Proc. Int. Symp. Asynchronous Circuits and Systems, 2000, pp. 114-125.
Martin, A. “Compiling communicating processes into delay-insensitive VLSI circuits,” Distributed Computing, 1986, 1(4).
Martin, A. J. “The limitations to delay-insensitivity in asynchronous circuits,” Technical Report Caltech-CS-TR-90-02, Department of Computer Science, California Institute of Technology, 1990.
McCardle J. et al. “Measuring an asynchronous processor's power and noise,” In Proc. Synopsys User Group Conference, 2001.
Rudell, R. L. “Logic Synthesis for VLSI Design,” PhD thesis, UCB/ERL M89/49, Electronics Research Laboratory, University of California at Berkeley, 1989.
Siegel, P. “Decomposition methods for library biding of speed-independent asynchronous designs,” In Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1994, pp. 558-565.
Siegel, P. et al. “Automatic technology mapping for generalized fundamental-mode asynchronous designs,” In Proc. ACM/IEEE Des. Autom. Conf., 1993, pp. 61-67.
Singh, N. P. “A design methodology for self-timed systems,” Technical Report MIT/LCS/TR-258, Laboratory for Computer Science, MIT, 1981, Master's thesis.
Smith, S. C. et al. “Optimization of NULL convention self-timed circuits,” Integration, the VLSI Journal, 2004, 37:135-165.
Sobelman, G. E. et al. “CMOS circuit design of threshold gate with hystersis,” In Proc. Int. Symp. Circuits Systems, 1998, pp. 61-64.
Spars, J. et al. “Design of delay insensitive circuits using multi-ring structures,” In Proc. European Des. Autom. Conf., 1992, pp. 15-20.
Van Berkel, C. H. et al. “Scanning the technology: Applications of asynchronous circuits,” Proc. IEEE, 1999, 87(2):223-233.
Van Berkel, K. et al. “Stretching quasi delay insensitivity by means of extended isochronic forks,” In Proc. Int. Symp. Asynchronous Circuits and Systems, 1995, pp. 99-106.
Van Berkel, K. et al. “VLSI programming of asynchronous circuits for low power,” Asynchronous Digital Circuit Design, 1995, pp. 151-210.
Wegener, I. “The Complexity of Boolean Functions,” John Wiley & Sons, and B. G. Teubner, 1987.
Yun, K. Y. et al. “Automatic synthesis of 3D asynchronous state machines,” In Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1992, pp. 576-580.
Zhou, Y. et al. “Cost-aware synthesis of asynchronous circuits based on partial acknowledgement,” In Proc. IEEE/ACM Int. Conf Computer-Aided Design, 2006.
De Micheli, G,Synthesis and Optimization of Digital Circuits, McGraw Hill, 1994.
Fant, K. M.,Logically-Determined Design. John Wiley & Sons, 2005.
Fuhrer, R. M,. and Nowick, S. M.,Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools, Kluwer Academic Publishers, 2001.
Muller, D.E., “Asynchronous logics and applications to information processing,” In H. Aiken and W. F. Main, editors,Switching Theory in Space Technology, pp. 289-297, Stanford University Press, 1963.
Seitz, C. L. System timing. In C. A. Mead and L. A. Conway, editors,Introduction to VLSI Systems, chapter 7. Addison-Wesley, 1980.
Smith, S.C. et al., “Delay-Insensitive Gate-level Pipelining,”Integration, The VLSI

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