Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-07-30
2008-11-04
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07448010
ABSTRACT:
A method for implementing virtual metal fill includes inserting metal fill data into a layout record based on one or more rules, extracting capacitance from the layout record to create a capacitance network, and reducing the capacitance network.
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Chiang Kuang-Wei
Lenahan Terrence A.
Cadence Design Systems Inc.
Garbowski Leigh Marie
Vista IP Law Group LLP
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