Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-07-30
2008-05-13
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07373620
ABSTRACT:
A method of extracting capacitance from a layout record includes imposing voltages on conductors in a layout record, and determining a total charge for each of the conductors to obtain a capacitor element for the conductors. A method of extracting capacitance from a layout record includes matching a configuration of conductors in a layout record against a reference pattern, and determining an extracted capacitance for the conductors based at least in part on the reference pattern. A method of extracting capacitance from a layout record includes providing a layout record of a circuit design, the layout record having data representing conductors and metal fill, and extracting capacitance to determine a set of capacitors between the conductors, the set of capacitors accounting for the metal fill.
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Bingham & McCutchen LLP
Cadence Design Systems Inc.
Chiang Jack
Tat Binh
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