Methods and compositions for post-etch layer stack treatment...

Details Methods and compositions for post-etch layer stack treatment... Methods and compositions for post-etch layer stack treatment...

1997-06-11

2001-04-03

Mills, Gregory (Department: 1763)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C438S725000, C438S714000, C438S734000, C216S049000

Reexamination Certificate

active

06209551

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of semiconductor integrated circuits (ICs). More particularly, the present invention relates to improved treatment of a wafer's layer stack using helium following metal etch.
In semiconductor IC fabrication, devices such as component transistors are formed on a semiconductor wafer or substrate, which is typically made of silicon. Metallic interconnect lines, which are etched from a metal layer disposed above the wafer, may then be employed to couple the devices together to form the desired circuit. These metal layers are typically made of aluminum, copper, or one of the known aluminum alloys. Metal etchants usually contain chlorine (Cl
2
), a highly selective aluminum etchant. Commonly used metal etchants may include, for example, BCl
3
/Cl
2
, HCl/Cl
2
and BCl
3
/Cl
2
/SF
6
, but any metal etch process that involves chloride or fluoride compounds may be employed.
The etched layer stack may then be subjected to a strip process to remove the photoresist (often polymeric in nature) applied prior to the metal etch to those areas of the layer stack which are not to be etched. Stripping may be conducted with a plasma asher. In this device, O
2
is excited into a plasma which dissociates the O
2
into various oxygen radicals and ion species that oxidize (ash) the photoresist. The volatile waste products formed by this ashing may then be exhausted away.
To facilitate discussion,
FIG. 1A
illustrates a cross-sectional view of a layer stack
100
, representing the layers formed during the processing of a typical substrate, e.g., one that may be employed to fabricate integrated circuits or flat panel displays.
FIG. 1A
depicts the layer stack after conventional metal etching has been completed, but before passivation and strip treatment. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of layer stack
100
, there is shown a substrate
102
, typically composed of Si. An oxide layer
104
, typically comprising SiO
2
, is formed above substrate
102
. As noted above, additional layers (not shown) may be interposed between the substrate
102
and the oxide layer
104
. One or more barrier layers
106
typically formed of Ti, TiN or other suitable barrier materials, may be disposed between oxide layer
104
and a subsequently deposited metal layer
108
. Barrier layer(s)
106
, when provided, functions to prevent the diffusion of silicon atoms from oxide layer
104
into the metal layer
108
.
Metal layer
108
typically comprises copper, aluminum or one of the known aluminum alloys such as Al—Cu, Al—Si, or Al—Cu—Si. For convenience, the metal layer
108
is referred to herein as the aluminum layer although it should be understood that such a reference may include a layer consisting of any of the aforementioned aluminum alloys. The remaining two layers of
FIG. 1
, i.e., an anti-reflective coating (ARC) layer
110
and an overlaying photoresist (PR) layer
112
, are then formed atop metal layer
108
. The ARC layer
110
, typically comprising TiN or other suitable material, helps prevent light (e.g., from the lithography step that patterns the photoresist) from being reflected and scattered off the surface of the metal layer
108
. Photoresist layer
112
represents a layer of conventional photoresist material (typically I-line), which may be patterned for etching, e.g., through exposure to ultra-violet rays. The layers of layer stack
100
are readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD).
To form the aforementioned metallic interconnect lines, a portion (indicated by arrow
115
) of the layers of the layer stack, including the metal layer, e.g., metal layer
108
, are etched in a suitable process. By way of example, one such process involves the patterning of a photoresist layer
112
by exposing the photoresist material in a lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, the areas of the metal layer that are unprotected by the mask are then etched away, leaving behind metal interconnect lines or features.
Following metal etch, a chlorine residue from the etch by-products may remain on the metal features of the layer stack. Unless it is removed, this chlorine residue may cause corrosion of the metal layer when the layer stack is exposed to air. Therefore, the layer stack is typically subjected to a passivation treatment using H
2
O or an H
2
O/O
2
mixture in a plasma environment in order to remove this chlorine residue. Such a typical conventional passivation process may result in the removal of chlorine etchant residue in approximately 60 s.
For illustrative purposes,
FIG. 1B
shows an expanded cross-sectional view of layer stack
100
of
FIG. 1A
after conventional etching, passivation and strip have been completed. The rate at which the photoresist is removed by the strip process is called the “strip rate.” In the figure, arrow
122
represents the photoresist removed by the conventional strip process. A typical conventional strip rate using pure H
2
O, for example, results in the removal of a typical photoresist layer
122
at, for example, about 1 micron per minute (&mgr;m/min).
A further parameter of the strip process is strip “uniformity.” Uniformity is a relative measure of strip rate across a wafer, typically obtained by the 1&sgr; method:
∑
(
&LeftBracketingBar;
r
i
-
r
_
&RightBracketingBar;
)
2
(
n
-
1
)
⁢
r
_
×
100
⁢
%
where r
i
is a measurement of the thickness of material removed at a particular point, i, on the wafer, {overscore (r)} is the average thickness of material removed at all measured points on the wafer, and n is the number of points at which measurements are taken. According to one variation of this method, forty-nine predetermined points on the wafer are measured pre- and post-ashing. Ideally, the strip rate should be as uniform as possible across the wafer so that strip time will be minimized.
Chlorine and other species with which the layer stack is bombarded during etching may modify the chemical composition of the sidewalls of the photoresist, so that the conventional strip process may be ineffective for its removal. As a result, a “polymer fence” composed of these modified photoresist sidewalls may remain following the strip process. This polymer fence
120
(as depicted, for example, in
FIG. 1B
) may be removed by a wet chemical process well known in the art in order to finish the semiconductor IC or prepare it for the next fabrication step.
While conventional passivation and strip processes have proven effective for semiconductor IC fabrication, improved passivation and strip processes which decrease the time necessary for passivation, increase the strip rate, and/or improve strip uniformity would be desirable.
SUMMARY OF THE INVENTION
The invention relates to improved treatment of a semiconductor wafer's layer stack following metal etch. The improved treatment includes passivation and/or strip processes and compositions including helium which decrease the time necessary for passivation, increase the strip rate, and/or improve strip uniformity.
One embodiment of the present invention is a method for treating a semiconductor wafer's layer stack following metal etching. The method involves providing a semiconductor wafer layer stack in a plasma processing system following metal etch, and treating the layer stack in one or more steps, with at least one process gas which contains helium and water and/or oxygen, or comparable gases. The method reduces corrosion and polymer fence for a wafer's layer stack relative to conventional treat

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