Methods and circuits for single-memory dynamic cell multivalue d

Static information storage and retrieval – Systems using particular element – Ternary

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365149, 365205, G11C 1156

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active

060057998

ABSTRACT:
A multivalue dynamic random access memory cell and method therefor are provided. Sense circuitry for sensing a most significant bit (MSB) and a least significant bit (LSB) of a binary data value are coupled to an unsegmented complementary bitline pair. The binary data is represented by a multilevel voltage stored on a storage element in the DRAM cell. A reference signal is provided to the sense circuitry, wherein the reference signal is independent of a precharge on the bitline pair. Cross-coupling elements offset the reference signal in response to the sensing of the MSB, whereby the voltage levels corresponding to the LSB are sensed. Following a read, the multilevel data value is restored on the storage element by a restore/write unit including a programmable voltage supply. The detected MSB/LSB pair are input to the restore/write unit which outputs the corresponding voltage level to the DRAM cell. A write is effected using the same restore/write unit with the binary datum to be stored input to the restore/write unit.

REFERENCES:
patent: 5729490 (1998-03-01), Calligaro et al.
patent: 5751634 (1998-05-01), Itoh
Okuda et al., A Four-Level Storage 4-Gb DRAM, IEEE Journal of Solid State Circuits, vol. 2, No. 11, pp. 1743-1747, Nov. 1997.

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