Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-22
2005-03-22
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06871335
ABSTRACT:
Described are methods for accurately measuring the skew of clock distribution networks on programmable logic devices. Clock distribution networks are modeled using a sequence of oscillators formed on the device using configurable logic. Each oscillator includes a portion of the network, and consequently oscillates at a frequency that depends on the signal propagation delay associated with the included portion of the network. The various oscillator configurations are defined mathematically as the sum of a series of delays, with the period of each oscillator representing the sum. The respective equations of the oscillators are combined to solve for the delay contribution of the included portion of the clock network. The delay associated with the included portion of the clock network can be combined with similar measurements for other portions of the clock network to more completely describe the network.
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U.S. Appl. No. 10/021,447, filed Oct. 30, 2001, Chan.
BBehiel Arthur
Liu Justin
Whitmore Stacy A.
XILINX Inc.
Young Edel M.
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