Methods and circuits for correcting a duty-cycle of a signal

Details Methods and circuits for correcting a duty-cycle of a signal Methods and circuits for correcting a duty-cycle of a signal

2001-04-05

2002-10-15

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S157000, C327S161000, C327S170000, C331SDIG002, C375S376000

Reexamination Certificate

active

06466071

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to duty-cycle correction, and more particularly to methods and circuits for reducing or preventing duty-cycle error.
BACKGROUND OF THE INVENTION
In digital clock applications, it may be important to precisely control the duty cycle of a clock signal. In general, a clock signal with a 50% duty-cycle is used in digital clock applications of a semiconductor integrated circuit. A duty cycle of 50% means that the high-level and low-level portions of the clock signal are identical. Therefore, a duty-cycle correction circuit may be used in digital clock applications to generate a clock signal having a duty-cycle of approximately 50%. When a clock signal whose duty-cycle is not at 50% is input to the duty-cycle correction circuit, the duty-cycle correction circuit converts the clock signal whose duty-cycle is not at 50% into a clock signal with a duty-cycle of approximately 50%.
Unfortunately, conventional duty-cycle correction circuit may generate duty-cycle distortion (i.e., duty-cycle error). Accordingly, it may be difficult to maintain a duty-cycle of a signal at approximately 50% using conventional circuits. Conventional duty-cycle correction circuits may comprise a slew-rate limiter, a differential amplifier, and an integrator. A representative circuit for duty-cycle correction is disclosed in U.S. Pat. No. 5,945,857 to Havens. When there is offset in the integrator, however, the duty-cycle correction circuit may generate duty-cycle distortion (i.e., duty-cycle error) due to the offset.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, a signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state. Advantageously, a signal may be duty-cycle corrected without using an integrator circuit, which may introduce duty-cycle error due to offset in the integrator. As a result, improved duty-cycle correction may be obtained.
The delayed version of the signal may be inverted to generate an inverted delayed version of the signal. Moreover, both the signal and the inverted delayed version of the signal may have their slew rates limited so as to generate first and second intermediate output signals, respectively. The output signal may then be generated by determining a voltage difference between the first and second intermediate output signals and generating the output signal responsive to the voltage difference.
The delayed version of the signal may be generated by determining a phase difference between the signal and the delayed version of the signal. A control voltage may be generated in response to the phase difference and the delayed version of the signal may be generated in response to the control voltage. The signal may be delayed for a predetermined time to generate the delayed version of the signal. In accordance with particular embodiments, the predetermined time may correspond to the time in which the signal is in the first state during a single cycle of the signal or a time in which the signal is in the second state during a single cycle of the signal.
In accordance with further embodiments of the present invention, a signal is duty-cycle corrected by limiting a slew rate of the signal to generate a first intermediate output signal. A voltage difference is determined between the first intermediate output signal and a reference voltage and an output signal is generated responsive to the voltage difference. The output signal is delayed to generate a delayed version of the output signal and the reference voltage is generated in response to the output signal and the delayed version of the output signal.
The delayed version of the output signal may be generated by determining a phase difference between the output signal and the delayed version of the output signal. A control voltage may be generated in response to the phase difference and the delayed version of the output signal may be generated in response to the control voltage. Furthermore, the reference voltage may be generated in response to a phase difference that is determined between the output signal and the delayed version of the output signal.
While the present invention has been described above primarily with respect to method aspects of the invention, it will be understood that the present invention may be embodied as methods and/or circuits.


REFERENCES:
patent: 5406590 (1995-04-01), Miller et al.
patent: 5572158 (1996-11-01), Lee et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 6084452 (2000-07-01), Drost et al.
Thomad H. Lee et al.; A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM; IEEE Journal of Solid-State Circuits, vol. 29, No. 12; Dec. 1994; pp. 1491-1496.
Bruno W. Garlepp et al.; A Portable Digital DLL for High-Speed CMOS Interface Circuits; IEEE Journal of Solid-State Circuits, vol. 34, No. 5; May 1999, pp. 632-644.

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