Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-01
2002-07-30
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S217000
Reexamination Certificate
active
06426534
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor fabrication, and in particular to mask-alignment test structures for measuring the alignment of superimposed elements formed on and within a semiconductor layer.
BACKGROUND
Most semiconductor devices are built up using a number of material layers. Each layer is patterned to add or remove selected portions to form circuit features that will eventually make up a complete integrated circuit. The patterning process, known as photolithography, defines the dimensions of the circuit features.
The goal of the patterning process is to create circuit features in the exact dimensions required by the circuit design and to place them in the proper locations on the surface of a semiconductor wafer. Perfect alignment is an ideal that cannot be achieved in practice. Instead, the various layers of an integrated circuit are misaligned to some extent. Such misalignment is termed “mask misalignment” because misaligned mask images are the source of the error. When circuits fail during fabrication, it is desirable to determine whether the source of the failure is incorrect mask alignment.
There are a number of conventional methods of detecting mask misalignment. For example, U.S. Pat. No. 5,770,995 to Masayuki Kamiya describes a structure that identifies misalignment between a conductive layer and a contact window layer. The disclosed structure indicates the direction of mask misalignment but does not provide an accurate measure of the extent of misalignment. Each of U.S. Pat. No. 4,386,459 to David Boulin and U.S. Pat. No. 4,571,538 to Pei-Ming Chow describe structures that indicate both the direction and extent of mask misalignment. The above-mentioned U.S. Patents provide useful background information, and are therefore incorporated herein by reference.
FIG. 1A
is a plan view of mask regions used to define a conventional MOS transistor
100
.
FIG. 1B
depicts MOS transistor
100
in cross section, taken along line A-A′ of
FIG. 1A. A
window
105
in an insulating layer
110
(
FIG. 1B
) serves as a mask to form the active regions of MOS transistor
100
. Window
105
might be formed, for example, along with similar windows in a field-oxide layer used to define active regions in a standard CMOS process. The term “active region” refers here to the area encompassing the source, drain, and channel regions of MOS transistor
100
in particular, and MOS transistors in general.
Modern semiconductor processes allow for precise adjustment of transistor threshold voltages. Threshold-voltage adjustments are made by altering the conductivity of transistor channel regions by implanting relatively low concentrations of dopants. N-channel and P-channel transistors require different dopant types and concentrations, so masks are used to expose the target areas and to shield other areas from inappropriate implants. These masks must therefore be properly aligned.
FIG. 1A
depicts the boundary
111
of an exemplary threshold-voltage implant;
FIG. 1B
depicts a threshold-voltage implant
112
.
After formation of threshold-voltage implant
112
, a gate
115
, and a gate insulator
120
are formed over the region defined within window
105
. Dopant atoms are then implanted in window
105
to create the source and drain regions.
FIG. 1A
depicts the boundary of an exemplary active-region implant
121
; the mask used to define boundary
121
must be aligned with window
105
. Gate
115
—typically polysilicon—masks the underlying substrate
117
, thus defining a channel region
122
between source and drain regions
125
and
130
. In modern CMOS processes, the active-region implant largely defines the dopant level in gate
115
, so that the conductivity type of gate
115
matches that of source and drain regions
125
and
130
for both PMOS and NMOS transistors.
Misalignment of the threshold-voltage implant mask produces very little change in resistance, and is therefore difficult to measure using alignment-measuring schemes that depend upon variations in resistance. Misalignment of the active-region implant is also difficult to measure using resistive means because salicide formations in the active regions greatly reduce the sheet resistance of the active regions, and therefore obscure resistance variations that result from misaligned active-implant masks. There is therefore a need for a mask-alignment detection structure that accurately indicates the direction and extent of misalignment for circuit features that produce little resistive variation when misaligned.
SUMMARY
The present invention satisfies the need for an accurate mask-alignment detection structure that measures both the direction and extent of misalignment between features of an integrated circuit. Measurements taking using structures in accordance with the invention are relatively insensitive to process variations, and the test structures can be formed along with other features on an integrated circuit using standard processes.
One embodiment of the invention measures the extent to which active-region implants are aligned with the areas on a semiconductor substrate in which the active regions are to be formed. One test structure in accordance with that embodiment is an MOS transistor that conventionally includes source and drain regions separated by a gate. A pair of active-region implants of a first conductivity type defines the source and drain regions, and an additional active-region implant of a second conductivity type extends over a portion of the gate. The additional active-region implant affects the threshold voltage of the affected portion of the gate; consequently, the gate exhibits two separate threshold voltages. The overall threshold voltage of the test structure is a function of the separate threshold voltages of the gate.
Misalignment of the active region implant in the gate changes the relative areas of the implanted and non-implanted portions of the gate, and consequently changes the overall threshold voltage of the test structure. The overall threshold voltage increases for misalignment in one direction and decreases with misalignment in the opposite direction. The threshold voltage of the test structure therefore provides a measure of alignment.
Another embodiment of the invention improves measurement accuracy by including a second test structure that mirrors the first test structure. Misalignment affects the two test structures in opposite ways, so the respective threshold voltages can be compared to determine the direction of misalignment. Process variations unrelated to alignment generally affect both test structures in the same way and therefore tend to cancel out.
Comparing the threshold voltages of two mirrored structures indicates whether and in what direction the active-region implants are misaligned; however, the difference between the threshold voltages can be difficult to correlate to an extent of misalignment. Another embodiment of the invention addresses this problem with an array of matching test-structure pairs. Each pair differs from the others in the relative areas of the implanted and non-implanted gate portions. When perfectly aligned, the threshold voltages of the test structures in each pair match, but the threshold voltages differ from one pair to the next. Misalignment causes the threshold voltages within each pair of test structures to diverge. The collection of diverging threshold-voltage values can be used to accurately determine the direction and extent of misalignment.
The structures and methods described above are easily adapted for use in measuring the alignment of threshold-voltage implants with respect to active regions. In one such embodiment, special threshold-voltage implants that extend beneath only a portion of the gate of an MOS transistor cause the transistor to have two channel areas with different threshold voltages. The resulting MOS transistor is much the same as the above-described test structure, and is similarly employed in pairs and arrays to detect and measure misalignment.
This summary does not purport to define
Hsueh Shih-Cheng
Look Kevin T.
Behiel, Esq. Arthur J.
Nelms David
Vu David
Xilinx , Inc.
Young Edel M.
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