Methods and arrangements to enhance a bus

Details Methods and arrangements to enhance a bus Methods and arrangements to enhance a bus

2006-06-27

2006-06-27

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S056000, C714S025000, C714S044000

Reexamination Certificate

active

07069477

ABSTRACT:
Methods and arrangements to enhance a bus are disclosed. Embodiments may test bus segments, device interfaces, couplings between devices and device interfaces for bit errors. Several embodiments generate a test signal in response to coupling a device to a device interface, transmit the test signal on the bus, and generate an error signal when the bus signal at the device interface is different from the anticipated bus signal. The test signal may comprise one or more patterns of bits configured to identify one or more faults associated with a bus segment, a bus switch of the device interface to isolate the adapter card from the bus, and circuitry or buffers of the adapter card as plugged into the slot of the device interface. In many of these embodiments, a bus signal is determined at the bus-side and/or slot-side of the device interface.

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