Methods and apparatuses to manage bandwidth mismatches...

Details Methods and apparatuses to manage bandwidth mismatches... Methods and apparatuses to manage bandwidth mismatches...

2004-11-02

2011-10-04

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S029000, C710S033000, C710S307000, C370S229000

Reexamination Certificate

active

08032676

ABSTRACT:
Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the communication fabric. The rate logic is configured to determine a data bandwidth difference between a first data bandwidth capability of the sending device and the lower of 1) a second data bandwidth capability of the sending device or 2) a third data bandwidth capability of the communication fabric.

REFERENCES:
patent: 5689659 (1997-11-01), Tietjen et al.
patent: 5699460 (1997-12-01), Kopet et al.
patent: 5734833 (1998-03-01), Chiu et al.
patent: 5745791 (1998-04-01), Peek et al.
patent: 5761348 (1998-06-01), Honma
patent: 5799203 (1998-08-01), Lee et al.
patent: 5802399 (1998-09-01), Yumoto et al.
patent: 5948089 (1999-09-01), Wingard et al.
patent: 6084934 (2000-07-01), Garcia et al.
patent: 6122690 (2000-09-01), Nannetti et al.
patent: 6182183 (2001-01-01), Wingard et al.
patent: 6205084 (2001-03-01), Akaogi
patent: 6233226 (2001-05-01), Gringeri et al.
patent: 6330283 (2001-12-01), Lafe
patent: 6393500 (2002-05-01), Thekkath
patent: 6678423 (2004-01-01), Trenary et al.
patent: 6725313 (2004-04-01), Wingard et al.
patent: 6785753 (2004-08-01), Weber et al.
patent: 6868459 (2005-03-01), Stuber
patent: 6891088 (2005-05-01), Neuhaus et al.
patent: 6970013 (2005-11-01), Cory
patent: 6981088 (2005-12-01), Holm et al.
patent: 7155554 (2006-12-01), Vinogradov et al.
patent: 7346040 (2008-03-01), Weinstein
patent: 2002/0038393 (2002-03-01), Ganapathy et al.
patent: 2002/0107903 (2002-08-01), Richter et al.
patent: 2002/0161848 (2002-10-01), Willman et al.
patent: 2003/0099254 (2003-05-01), Richter
patent: 2003/0191884 (2003-10-01), Anjo et al.
patent: 2003/0212743 (2003-11-01), Masri et al.
patent: 2004/0017820 (2004-01-01), Garinger et al.
patent: 2005/0210164 (2005-09-01), Weber et al.
patent: 2005/0216641 (2005-09-01), Weber et al.
patent: 2006/0092944 (2006-05-01), Wingard et al.
patent: 2006/0095635 (2006-05-01), Vinogradov et al.
patent: 1179785 (2002-02-01), None
patent: 63296158 (1988-12-01), None
patent: WO 2004008329 (2004-01-01), None
Culler, David E.: “Split-Phase Busses,” CS 258, Computer Science Division, U.C. Berkely, Spring 1999, pp. 1-23.
International Search Report, PCT/US2005/008239, mailed Jun. 13, 2005, 3 pp.
International Search Report, PCT/US2005/008235, mailed Nov. 30, 2005, 6 pp.
AMBA 3.0 (AMABA AXI).
MIPS32 24 K Family of Synthesizable Processor Cores, Product Brief, MIPS Technologies.
Open Core Protocol Monitor, Data Sheet, Mentor Graphics.
IP Core-Centric Communications Protocol Introducing Open Core Protocol 2.0, www.design-reuse.com.
Enabling Reuse Via an IP Core-Centric Communications Protocol: Open Core Protocol, Wolf-Dietrich Weber, Sonics, Inc.
NECoBus: A High-End SOC Bus with a Portable & Low-Latency Wrapper-Based Interface Mechanism, Anjo et al., NEC Corporation, IEEE 2002.
Open Core Protocol Specification, Release 2.0, pp. 1-3, 31-57, copyright 2003.
Socket-Centric IP Core Interface Maximizes IP Applications, www.ocpip.org.
Definition of Burst Mode Access and Timing, www.pcguide.com.
Definition of Direct Memory Access (DMA) Modes and Bus Mastering DMA, www.pcguide.com.
Definition of PCI Bus Performance, www.pcguide.com.
Weiss, Ray, “PCI-X Exposed,” TechOnLine, http://www.techonline.com/community/ed—resource/feature—article/7114, Jun. 28, 2005, 3 pages.
Wolf, Tilman et al., “Design Tradeoffs for Embedded Network Processors”, Department of Computer Science Washington University, Jul. 10, 2000, 17 pages.
McGrath, Joel, “The Need for Package-Aware Methodology for IC Design”, Chip Design Magazine, Mar. 20, 2006, 5 pages.

Affiliated with

Also associated with

Rating

Methods and apparatuses to manage bandwidth mismatches... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatuses to manage bandwidth mismatches..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatuses to manage bandwidth mismatches... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4259819