Methods and apparatuses to clear state for operation of a stack

Details Methods and apparatuses to clear state for operation of a stack Methods and apparatuses to clear state for operation of a stack

2001-02-16

2004-06-15

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S222000, C712S004000, C712S213000, C708S204000

Reexamination Certificate

active

06751725

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of computer systems. More specifically, the invention relates to the execution of floating point and packed data instructions by a processor.
2. Background Information
In a typical computer system, one or more processors operate on data values represented by a large number of bits (e.g., 16, 32, 64, etc.) to produce a result in response to a programmed instruction. For example, the execution of an add instruction will add a first data value and a second data value and store the result as a third data value. However, multimedia applications (e.g., applications targeted at computer supported cooperation (CSC—the integration of teleconferencing with mixed media data manipulation), 2D/3D graphics, image processing, video compression/decompression, recognition algorithms and audio manipulation) require the manipulation of large amounts of data which is often represented by a smaller number of bits. For example, multimedia data is typically represented as 64-bit numbers, but only a handful of bits may carry the significant information.
To improve efficiency of multimedia applications (as well as other applications that have the same characteristics), prior art processors provide packed data formats. A packed data format is one in which the bits used to represent a single value are broken into a number of fixed sized data elements, each of which represents a separate value. For example, data in a 64-bit register may be broken into two 32-bit elements, each of which represents a separate 32-bit value.
Hewlett-Packard's basic 32-bit architecture machine took this approach to implementing multi-media data types. That is, the processor utilized its 32-bit general purpose integer registers in parallel to implement 64-bit data types. The main drawback of this simple approach is that it severely restricts the available register space. Additionally, the performance advantage of operating on multimedia data in this manner in view of the effort required to extend the existing architecture is considered minimal.
A somewhat similar approach adopted in the Motorola® 88110 processor is to combine integer register pairs. The idea of pairing two 32-bit registers involves concatenating random combinations of specified registers for a single operation or instruction. Once again, however, the chief disadvantage of implementing 64-bit multi-media data types using paired registers is that there are only a limited number of register pairs that are available. Short of adding additional register space to the architecture, another technique of implementing multimedia data types is needed.
One line of processors which has a large software and hardware base is the Intel Architecture family of processors, including the Pentium® processor, manufactured by Intel Corporation of Santa Clara, Calif.
FIG. 1
shows a block diagram illustrating an exemplary computer system
100
in which the Pentium processor is used. For a more detailed description of the Pentium processor than provided here, see
Pentium Processor's Users Manual—Volume
3:
Architecture and Programming Manual,
1994, available from Intel Corporation of Santa Clara, Calif. The exemplary computer system
100
includes a processor
105
, a storage device
110
, and a bus
115
. The processor
105
is coupled to the storage device
110
by the bus
115
. In addition, a number of user input/output devices, such as a keyboard
120
and a display
125
, are also coupled to the bus
115
. A network
130
may also be coupled to bus
115
. The processor
105
represents the Pentium processor. The storage device
110
represents one or more mechanisms for storing data. For example, the storage device
110
may include read only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices, and/or other machine-readable mediums. The bus
115
represents one or more busses (e.g., PCI, ISA, X-Bus, EISA, VESA, etc.) and bridges (also termed as bus controllers).
FIG. 1
also illustrates that the storage device
110
has stored therein an operating system
132
for execution on the processor
105
. Of course, the storage device
110
preferably contains additional software (not shown).
FIG. 1
additionally illustrates that the processor
105
includes a floating point unit
135
and a floating point status register
155
(the notation “FP” is used herein to refer to the term “floating point”). Of course, the processor
105
contains additional circuitry which is not necessary to understanding the invention.
The floating point unit
135
is used for storing floating point data and includes a set of floating point registers (also termed as the floating point register file)
145
, a set of tags
150
, and a floating point status register
155
. The set of floating point registers
145
includes eight registers labeled RØ to R
7
(the notation Rn is used herein to refer to the physical location of the floating point registers). Each of these eight registers is 80 bits wide and contains a sign field (bit
79
), an exponent field (bits [
78
:
64
]), and a mantissa field (bits [
63
:
0
]). The floating point unit
135
operates the set of floating point registers
145
as a stack. In other words, the floating point unit
135
includes a stack referenced register file. When a set of register is operated as a stack, operations are performed with reference to the top of the stack, rather than the physical locations of the registers in the set of floating point registers
145
(the notation STn is used herein to refer to the relative location of the logical floating point register n to the top of the stack). The floating point status register
155
includes a top of stack field
160
that identifies which register in the set of floating point registers
145
is currently at the top of the floating point stack. In
FIG. 1
, the top of stack indication identifies a register
165
at physical location R
4
as the top of the stack.
The set of tags
150
includes 8 tags and is stored in a single register. Each tag corresponds to a different floating point register and comprises two bits. As shown in
FIG. 1
, tag
170
corresponds to register
165
. A tag identifies information concerning the current contents of the floating point register to which the tag corresponds—00=valid; 01=zero; 10=special; and 11=empty. These tags are used by the floating point unit
135
to distinguish between empty and non-empty register locations. Thus, the tags can be thought of as identifying two states: empty which is indicated by 11, and non-empty which is indicated by any one of 00, 01, or 10.
These tags may also be used for servicing events. An “event” is any action or occurrence to which a computer system might respond, including hardware interrupts, software interrupts, exceptions, faults, traps, aborts, machine checks, assists, and debug events. Upon receiving an event, the processor's event handling mechanism causes the processor to interrupt execution of the current process, store the interrupted process' execution environment (i.e., the information necessary to resume execution of the interrupted process), and invoke the appropriate event handler to service the event. After servicing the event, the event handler causes the processor to resume the interrupted process using the process' previously stored execution environment. Programmers of event handlers may use these tags to check the contents of the different floating registers in order to better service an event.
While each of the tags have been described as containing two bits, alternative embodiments could store only one bit for each tag. Each of these one bit tags identifying either empty or non-empty. In such embodiments, these one bit tags may be made to appear to the user as comprising two bits by determining the appropriate two bit tag value when the tag values are needed.
The status register
140
includes an EM f

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