Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2011-05-10
2011-05-10
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
C716S101000, C716S104000, C716S113000, C369S013070
Reexamination Certificate
active
07941779
ABSTRACT:
Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit to optimize the design. A thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature dependent power dissipation. Then, the components of the design are selectively transformed to reduce the power dissipation and to improve timing based on the temperature solution. The transformation may include placement changes and netlist changes, such as the change of transistor threshold voltages for cells or for blocks of the circuit chip.
REFERENCES:
patent: 5682320 (1997-10-01), Khouja et al.
patent: 6331966 (2001-12-01), Minami et al.
Kaustav Banerjee, et al. “Analysis and Optimization of Thermal Issues in High-Performance VLSI”, Proceedings of 2001 International Symposium on Physical Design (ISPD), Apr. 2001, pp. 230-237, Sonoma, California.
Kyoung Keun Lee, et al. “Thermal-driven Circuit Partitioning and Floorplanning with Power Optimization”. Georgia Institute of Technology, Center for Experimental Research in Computer Systems, Technical Reports, GIT-CERCS-03-07, 2003, 7 pages.
Guoqiang Chen, et al. “Partition-Driven Standard Cell Thermal Placement”, Proceedings of 2003 International Symposium on Physical Design (ISPD), Apr. 2003. pp. 75-80. Monterey, California.
Farid N. Najm. “A Survey of Power Estimation Techniques in VLSI Circuits”. IEEE Trans. on VLSI, Dec. 1994, pp. 1-21.
Shamik Das, et al. “Timing, Energy, and Thermal Performance of Three-Dimensional Integrated Circuits”, Proceedings of Great Lakes Symposium on VLSI (GL VLSI), Apr. 2004, 6 pages, Boston, Massachusetts.
Osman S. Unsal, et al. “System-Level Power-Aware Design Techniques in Real-Time Systems”. Proceedings of the IEEE, vol. 91, No. 7, Jul. 2003.
Kaushik Roy, et al. “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”, Proceedings of the IEEE, Feb. 2003, pp. 305-327, vol. 91, No. 2.
Pillage, L. T., et al., “Sparse Tableau Analysis”, Electronic Circuit of System Simulation Methods, Dec. 1994, pp. 200-204, Chapter 7.6.
Tsai, Ching-Han, et al., “Standard Cell Placement for Even On-Chip Thermal Distribution”, Proceedings of 1999 International Symposium on Physical Design (ISPD), 1999, 6 pages.
McElvain Kenneth S.
Rahmat Khalid
Blakely , Sokoloff, Taylor & Zafman LLP
Do Thuan
Synopsys Inc.
Szepesi Judith A.
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