Methods and apparatuses for reducing step loads of processors

Details Methods and apparatuses for reducing step loads of processors Methods and apparatuses for reducing step loads of processors

2011-08-02

2011-08-02

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S323000, C713S340000, C712S205000, C712S206000

Reexamination Certificate

active

07992017

ABSTRACT:
Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

REFERENCES:
patent: 5991884 (1999-11-01), Lin et al.
patent: 2003/0105901 (2003-06-01), Wolrich et al.
patent: 2005/0138450 (2005-06-01), Hsieh
patent: 2006/0005082 (2006-01-01), Fossum et al.

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