Methods and apparatuses for nonvolatile memory wear leveling

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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C711S202000, C711S203000, C711S165000, C711SE12008

Reexamination Certificate

active

07917689

ABSTRACT:
Apparatuses, systems, and computer program products that enable wear leveling of nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments an apparatus that has a receiver and a wear leveling module. The receiver may receive low-level write requests to update direct-mapped values of nonvolatile memory. The wear leveling module may determine physical locations of the nonvolatile memory that correspond to logical locations of the write requests. Alternative embodiments may comprise systems or apparatuses that include one or more various types of additional modules, such as low-level driver modules, error correction code modules, queue modules, bad block management modules, and flash translation layer modules. Other embodiments comprise computer program products that receive a direct-mapped low-level write request, determine a physical write location of nonvolatile memory that corresponds to a logical write location of the low-level write request.

REFERENCES:
patent: 2008/0140918 (2008-06-01), Sutardja
patent: 2008/0189485 (2008-08-01), Jung et al.
Hyde; Randall. “I/O Mechanisms.” Write Great Code: Understanding the Machine. 2004. p. 334.
Godse, A. P.; and Godse, D. A. “I/O Interfacing Techniques in 8086.” Microprocessors and Microcontrollers. Technical Publications Pune. 2009. Three pages.

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