Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2000-10-23
2004-10-19
Gaffin, Jeffrey (Department: 2183)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S033000, C710S035000, C710S030000, C711S152000, C711S154000
Reexamination Certificate
active
06807587
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to direct memory access (DMA) data transfers, and more specifically to coherent and efficient transfers of buffered DMA data.
BACKGROUND
Direct memory access (DMA) is a method of transferring data without the intervention of the microprocessor. This allows for memory to be accessed without a negative impact on system performance. DMA data transfers are used for data transfers between input/output (IO) devices and memory and also for memory-to-memory data transfers. DMA data transfers, when not buffered, suffer from the limitation that only one piece of data is transferred at a time. When a system has an external memory that is wider than the source or destination of the data being transferred, the memory subsystem is not used to full capacity in transferring data. For example, if the external memory is 32 bits wide and the source or destination of the transferred data is only 8 bits wide then only 8 bits can be transferred at a time. This method does not make full use of the memory subsystem that could handle a 32 bit wide transfer. Further, non-buffered DMA data transfers cannot always take advantage of the burst mode read or write, a capability of dynamic random access memory (DRAM) which maximizes memory bandwidth.
Buffering the DMA data resolves the problem of maximizing the capabilities of the memory subsystem and maximizing memory bandwidth by taking advantage of the burst mode capability of DRAM, but not without a considerable drawback. Buffered DMA data suffers from a lack of coherency. Coherency in this sense means that data intended to be written to a memory location will be correctly read from that location at a future time. When DMA data is buffered during transfer, the coherency of the data may be jeopardized as follows. When the DMA data is being transferred from, for example, an IO device, but has not yet been written out to the desired memory location, portions of the data are stored in a write buffer. If there is an attempt to read during this time, the data may not be correct. That is, while data for some memory locations is temporarily held in the write buffer, an attempted read operation to those locations will return data previously written to those locations.
This lack of data coherency in buffered DMA data transfers is dealt with in several ways. A simple method is to prevent any read from taking place while there is data stored in the write buffer. This method is used in a cached microprocessor system using a write-through strategy and a write buffer. If a read is attempted the write buffer is flushed first and then the read is allowed to take place. This method has a considerable impact on system performance. If no read can occur while the write buffer contains any data, the detrimental impact on system performance is nearly equivalent to a non-buffered DMA data transfer system.
A more sophisticated method of dealing with the effect on data coherency in buffered DMA data transfers is to include circuitry to keep track of which memory address locations the data in the write buffer will be written to. The addresses are then compared with the addresses of the current read operation. If a match occurs between the addresses, then the corresponding data for that address which is in the write buffer will be returned in response to the read operation. If a match does not occur, then the data stored in the memory address will be returned in response to the read operation. The drawback of this method is that the process of matching the read addresses with the addresses in the write buffer requires extra registers to hold the address ranges and circuitry capable of rapidly comparing addresses. The design is similar to a cache in complexity and increases the area requirements significantly.
Another method of avoiding the data coherency problem is to manage the DMA data transfers with software control. The DMA unit (DMAU) communicates with the microprocessor system in order to establish the end of a DMA data transfer. One such communication mechanism is the use of interrupts. The software must make sure that the data is not read while the DMA is active and must also make sure that the data is safe to be read after the write buffer is empty. This method relies on the DMAU having repeated contact with the microprocessor, and, to some degree, defeats the purpose of DMA data transfers (i.e. direct access) and adversely affects system performance.
Locking the DMA channel is another method of ensuring the coherency of DMA transfer data through the interaction of the system components. The DMAU communicates with the memory sub-system. The DMAU monitors the write buffer and will not initiate another DMA data transfer until all the data in the write buffer has been written to memory. In this situation the DMA will not specifically inform the CPU, or other bus master, that the transfer is complete until the memory subsystem lets the CPU know that the buffer has been flushed. The memory subsystem indicates the buffer has been flushed with a dedicated signal. This scheme does not tax the microprocessor to the extent the software control method described above. Nevertheless, there is a major drawback. There are dedicated signals between the DMAU and the memory subsystem that allow the DMA channel to be locked while data is being written out from the write buffer to memory. This requires each DMAU to work exclusively with a particular memory subsystem, severely limiting the flexibility of the system. Thus, the DMAU is a less generic implementation.
SUMMARY OF THE INVENTION
A method is described for transferring data to memory. A last write data indicator is included in the data as the last piece of data to be transferred. The data is transferred to a write buffer and the last write data indicator is received by the write buffer. If a memory request occurs, a wait line is asserted such that memory operations (i.e., reading from, or writing to, the memory) are prevented for all sources other than the DMA channel associated with the “Last Write Data” signal. All data within the write buffer is transferred to the memory after the last write data indicator is received by the write buffer. This data transfer method maintains the coherency of the transferred data with minimal impact on system performance.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 5915104 (1999-06-01), Miller
patent: 6311234 (2001-10-01), Seshan et al.
patent: 6336154 (2002-01-01), McCarthy et al.
patent: 6370625 (2002-04-01), Carmean et al.
patent: 6438628 (2002-08-01), Messerly et al.
patent: 6496905 (2002-12-01), Yoshioka et al.
Allegrucci Jean-Didier
Murray James
Blakely & Sokoloff, Taylor & Zafman
Gaffin Jeffrey
Patel Niketa
Xilinx , Inc.
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