Methods and apparatuses for checking equivalence of circuits

Details Methods and apparatuses for checking equivalence of circuits Methods and apparatuses for checking equivalence of circuits

2001-10-29

2004-02-10

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C702S109000, C703S015000

Reexamination Certificate

active

06691286

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of designing (e.g. verifying) integrated circuits and, more particularly, to the design of integrated circuits which may be modified or optimized during a design process.
BACKGROUND OF THE INVENTION
For the design of digital circuits on the scale of VLSI (Very Large Scale Integration) technology, designers often employ computer aided techniques. Standard languages such as hardware description languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL), or the behavioral level using abstract data types. As device technology and design technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles and to also allow for the optimization of a design after the compilation of an HDL code which describes a particular circuit.
FIG. 1
shows an example in the prior art in which a circuit is initially designed and then optimized in the design process. The optimized design typically must be compared with the original design to verify that the optimized design is equivalent to the initial or original design. This is often required because the optimization process may result in a change to the design which causes the second design (e.g. an optimized design) to not be an equivalent circuit such that the optimized design does not produce the same result for a given input as the initial design. The process of
FIG. 1
begins in step
10
in which an HDL code is prepared for a particular circuit. This code is typically compiled in an HDL compiler to generate a first RTL representation. This is shown as process element
12
. Then in process element
14
, the first RTL representation is processed in order to optimize the design which results in a second RTL representation. Then in process element
16
, a verification tool, such as a commercially available verification software product, is used to check for equivalence between the first RTL representation and the second RTL representation. In process element
18
, the use of this tool results in a test to determine whether the two representations are equivalent. If these two representations are not equivalent, this results in an error message being displayed to the designer by the verification tool in process element
19
. On the other hand, if the verification tool can verify that the two representations are equivalent, then an indication of this equivalence is displayed to the designer and the process may proceed to process element
20
in which place and route tools are used to create an integrated circuit from the second RTL representation.
Present verification tools have very little ability to handle optimizations, particularly sequential optimizations, such as the first RTL representation. For example, these optimizations may include in sequence, sequential redundancy removal, state machine re-encoding, flip-flop replication, retiming, pipelining, half-cycle scheduling, and conversions between clock gating and enables. Thus the verification tools which exist in the prior art, when used in process element
16
discussed above, typically fail to verify the equivalence between the initial circuit and an optimized version of the circuit even when they are equivalent. Thus, too many error messages result (process element
19
of FIG.
1
), resulting in increased cost and delay in designing the desired integrated circuit.
SUMMARY OF THE INVENTION
The present invention discloses methods and apparatuses for designing (e.g. verifying) one or more integrated circuits. According to one aspect of the present invention, an exemplary method for designing an integrated circuit includes identifying a first plurality of points in a first representation of a circuit which represents the integrated circuit, and modifying the first representation to produce a second representation which differs from the first representation, and maintaining a list of changes made during the modifying (wherein the list includes at least one change caused by the modifying), and identifying, from the list, a correspondence between a second plurality of points in the second representation and the first plurality of points (e.g. an association between a subset of the first plurality of points and a subset of the second plurality of points). According to this exemplary method, the first representation is compared with the second representation at the first plurality of points and the second plurality of points, and this comparison indicates whether the first representation is equivalent to the second representation.
According to another aspect of the invention, an exemplary method of designing an IC includes modifying a first representation, which represents at least a portion of the IC, to produce a second representation which differs from the first representation, and determining an initialization sequence for the first representation, and determining first simulated states for the first representation, where the first simulated states are derived from the initialization sequence over a plurality of simulated clock cycles, and comparing the first representation with the second representation in order to determine whether the first representation is equivalent to the second representation.
The present invention also discloses apparatuses, including software media which may be used to design integrated circuits. For example, the present invention includes digital processing systems which are capable of designing integrated circuits according to the present invention, and the invention also includes machine readable media, which when executed on a digital processing system such as a computer system, causes the digital processing system to execute a method for designing integrated circuits.


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Rajeev K. Ranjan, et al., “Using Combinational Verification for Sequential Circuits,”Proceedings on Conference on Design Automation and Test(Europe) 1999, pp. 1-10.

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