Methods and apparatuses for binning partially completed integrat

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257210, 257211, 257758, 257797, 324765, 324769, 438 11, H01L 2358

Patent

active

061335827

ABSTRACT:
A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer's performance and/or yield requirements. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer. Further, a programmable gate array integrated circuit which has features for testing and binning for speed and performance grading prior to final personalization or programming on the top layer or layers of interconnecting material is provided.

REFERENCES:
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5206181 (1993-04-01), Gross
patent: 5631478 (1997-05-01), Okumura
patent: 5640049 (1997-06-01), Rostoker et al.
patent: 5654204 (1997-08-01), Anderson
patent: 5726458 (1998-03-01), Bui
patent: 5861660 (1999-01-01), Mc Clure
patent: 5917197 (1999-06-01), Alswede et al.
patent: 5956566 (1999-09-01), Lin et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods and apparatuses for binning partially completed integrat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatuses for binning partially completed integrat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatuses for binning partially completed integrat will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-471560

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.