Electrical computers and digital data processing systems: input/ – Interrupt processing – Multimode interrupt processing
Reexamination Certificate
1999-08-13
2002-03-12
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Interrupt processing
Multimode interrupt processing
C710S262000, C710S263000, C710S264000, C710S266000, C710S048000, C710S006000, C711S114000
Reexamination Certificate
active
06356969
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to intelligent peripheral devices, and more particularly to intelligent peripheral devices using interrupt score boarding to reduce interrupts to the primary processor.
The management of a number of peripheral devices presents difficulties in providing improved processor performance with a manageable amount of overhead. This is particularly the case for the management of the multiple input/output (I/O) tasks which is inherent in processing RAID operations for future generation RAID storage subsystems. This is due in part to the significant microprocessor overhead required to manage the large number of I/O tasks. In particular, a typical RAID read/modify/write command can require as many as six (6) or more individual I/O tasks. As one skilled in the art will appreciate, with the RAID controller designs currently known in the art, the controller's microprocessor typically must manage all these I/O tasks as they occur. The routines required to manage the RAID hardware set-up and the interrupt service threads for each of the individual RAID I/O tasks result in inefficient interruption of the microprocessor and thrashing of the microprocessor primary and secondary cache.
It is desirable, therefore, to significantly reduce the number of interrupts that the primary processor must handle to improve processor performance.
SUMMARY OF THE INVENTION
The present invention provides novel apparatus and methods for using interrupt score boarding with intelligent peripheral devices. This invention is particularly useful for building high throughput/low latency storage system controllers.
In one embodiment, the present invention provides a storage system controller having a main processor, a memory and a device interface adapted to interface with a peripheral component, such as a disk array or the like. The controller further includes an interrupt management scoreboard adapted to receive a plurality of writes from the peripheral component prior to interrupting the main processor. In this manner, the scoreboard facilitates the reduction of interrupts to the main processor by receiving writes, such as operation completion updates, instead of having the peripheral components directly interrupt the main processor. For example, in one aspect, the plurality of writes include a plurality of status messages and/or a plurality of interrupts.
In alternative aspects, the scoreboard may include a co-processor fabricated on the same chip as the main processor, or a co-processor in electrical communication with the main processor via a bus. Alternatively, the scoreboard may include at least one register within the main processor.
In one aspect, the peripheral component includes a storage media for use with a RAID controller, although a wide range of peripheral components may be used within the scope of the present invention. For example, the peripheral component may include a storage array, an optical disk drive, just a bunch of disks (JBOD), and the like. In another aspect, the controller has a plurality of device interfaces adapted to interface with a plurality of peripheral components.
The present invention further provides exemplary methods of controlling a storage system. One particular method includes the step of providing a storage system controller having a main processor, a memory, a device interface, and an interrupt management scoreboard. A peripheral component is provided to be in electrical communication with the controller via the device interface. The method includes determining a group of tasks to be executed prior to interrupting the main processor, setting up the interrupt management scoreboard, and sending the group of tasks to the peripheral component. The group of tasks are executed and the peripheral component or the device interface issues a write to the scoreboard after the peripheral component executes each of the tasks within the group of tasks. The method further includes interrupting the main processor after the one or more peripheral components or the one or more device interfaces has issued a group of writes corresponding to the group of tasks to the scoreboard. In this manner, the main processor identifies a desired group of tasks to be completed before the main processor needs to be interrupted. The main processor uses the scoreboard to ensure that all of the tasks of an operation are completed before the main processor is interrupted.
In one aspect, the device interface includes a plurality of device interfaces and the peripheral component includes a plurality of peripheral components. Tasks within the group of tasks are then sent to the plurality of peripheral components as appropriate. In one aspect, the device interface includes an intelligent device interface, for example a device interface having intelligent I/O capabilities.
In one particular aspect, the step of setting up the scoreboard includes setting up at least one register within the main processor to receive the group of writes. In this manner, the step of interrupting the main processor involves the main processor reading the scoreboard. Alternatively the interrupting step includes an intelligent device, such as the peripheral component or an intelligent device interface issuing an interrupt to the main processor when all of the scoreboard writes are complete.
In an alternative method of controlling a storage system of the present invention, the method includes the steps of providing a storage system controller and a peripheral component as previously described. A group of N tasks are identified to be executed prior to interrupting the main processor. The interrupt management scoreboard is set up, and the group of N tasks are sent to the peripheral component(s). Preferably, the steps of identifying the group of N tasks and setting up the scoreboard are performed by the main processor.
The method includes executing a first task within the group of tasks with the peripheral component. After the first task executes, a first write is issued to the scoreboard. If an error occurs during the processing of the first task, the main processor may be interrupted with an error message. Otherwise, the second through Nth tasks within the group of tasks are executed, with 2nd through Nth writes to the scoreboard upon successful completion of each task. The main processor may be interrupted in the event one of the tasks ends in an error. Assuming no errors, the main processor is interrupted after the peripheral component(s) has issued a group of writes corresponding to the group of tasks to the scoreboard. In other words, the main processor is interrupted after the successful completion of the group of N tasks that were identified and grouped to be executed prior to interrupting the main processor.
Alternatively, first through Nth writes are written to the scoreboard prior to interrupting the main processor. Each write is an error message if the corresponding task is unsuccessfully executed, or a completion message if the corresponding task is successfully executed. After first through Nth writes to the scoreboard corresponding to the at least attempted execution of the N tasks, the main processor is interrupted.
In one particular aspect, at least one register is set up within the main processor to receive the group of writes. Alternatively, the scoreboard can be external to the main processor as previously described. In another aspect, the interrupt is issued to the main processor by the peripheral component or by an intelligent device interface. In this manner, the intelligent peripheral component and/or the device interface can interrupt the main processor when an error is encountered.
A more complete understanding of the present invention may be derived by referring to the detailed description of preferred embodiments and claims when considered in connection with the figures, wherein like reference numbers refer to similar items throughout the figures.
REFERENCES:
patent: 5179704 (1993-01-01), Jibbe et al.
patent: 5671365 (1997-09-01), Binford et al
DeKoning Rodney A
Gates Dennis E.
Holt Keith W.
Kloeppner John R.
LSI Logic Corporation
Shin Christopher B.
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