Methods and apparatus for transferring cache block ownership

Details Methods and apparatus for transferring cache block ownership Methods and apparatus for transferring cache block ownership

2002-01-24

2004-08-10

Sparks, Donald (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S141000, C711S144000, C711S145000, C711S146000, C711S128000, C711S143000

Reexamination Certificate

active

06775748

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to cache memory and, in particular, to methods and apparatus for transferring cache block ownership.
BACKGROUND
In an effort to increase computational power, many computing systems are turning to multi-processor systems. A multi-processor system typically includes a plurality of microprocessors, a plurality of associated caches, and a main memory. In an effort to reduce bus traffic to the main memory, many multi-processor systems use a “write-back” (as opposed to a “write-through”) policy. A “write-back” policy is a cache procedure whereby a microprocessor may locally modify data in its cache without updating the main memory until the cache data needs to be replaced. In order to maintain cache coherency in such a system, a cache coherency protocol may be used.
In an effort to further reduce bus traffic to the main memory, many of these cache coherency protocols allow a first cache that is holding locally modified data (i.e., “dirty” data) to directly supply a second cache that is requesting the same block, without updating main memory. Typically, the first cache then puts its memory block in an “owned” state to indicate that the block is “dirty” and shared. However, when the “owned” block is replaced, the first cache must write the block back to main memory so that the modifications are not lost. This write-back generates bus traffic to the main memory. Bus traffic increase memory latency and power consumption. Subsequent modifications to the memory block in the second cache will also need to be written-back to main memory, thereby generating additional bus traffic.


REFERENCES:
patent: 5664150 (1997-09-01), Isaac et al.
patent: 5913226 (1999-06-01), Sato
patent: 6438660 (2002-08-01), Reams
patent: 6549990 (2003-04-01), Hughes et al.
patent: 6615322 (2003-09-01), Arimilli et al.

Affiliated with

Also associated with

Rating

Methods and apparatus for transferring cache block ownership does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatus for transferring cache block ownership, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for transferring cache block ownership will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3328820