Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1997-07-15
2003-01-07
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754120, C250S310000
Reexamination Certificate
active
06504393
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods and apparatus for testing semiconductor structures such as those found in integrated circuits. In particular, the invention provides techniques by which finished or part-finished semiconductor wafers can be tested during the manufacturing process.
BACKGROUND OF THE INVENTION
Electron beam systems based on the voltage contrast principle have been developed for detecting open and short faults of conductors on multichip-module (NCM) substrates (see for example U.S. Pat. No. 4,415,851, U.S. Pat. No. 4,417,203 and U.S. Pat. No. 4,443,278) and flat panel displays. The basic operational principle is that the circuit conductor voltage can be determined from the intensity of the detected secondary electrons (“voltage contrast”); given this information it is possible to find open and short faults in the circuit patterns. In the examples given above, an electron beam is used to charge up a net (a chain of connected nodes) and the voltages on the nodes in this net or the nodes in the neighboring nets are subsequently examined. Since all nodes in the charged net are expected to charge up, any non-charged nodes indicate open faults. On the other hand, any charged up nodes in the near-by nets signal short faults. In case of testing flat panel displays, an electron beam is used to charge each pixel cell and the equilibrium potential is determined. Two different types of defects can be detected: open- or short-pixel. An open-pixel has a higher final charging potential when compared to a normal pixel while a short-pixel has a lower final charging potential.
Electron-beam voltage contrast has also been demonstrated for detecting open and short faults on unfinished semiconductor wafers which are invisible to optical inspection systems. To prevent beam-induced damage of the wafer, a low voltage beam has to be used. A high voltage beam will cause beam penetration damage and can charge the surface to a harmful high voltage; a low voltage beam, on the other hand, charges the surface positively, and the charging mechanism is self regulated to less than a few volts. A voltage contrast image shows distinction between floating metal lines (charged up positively) and grounded metal line to the substrate (uncharged). Because this system can only differentiate the two states, the detectable defects can be generalized into two types: should-be floating metal lines that are grounded because of a bad short to the substrate, or should-be grounded metal lines that are floating because of a broken connection. This technique is most suitable for detecting defects in circuit patterns which contain a mixture of floating and grounding conductors; which is often the case at the late stage of the fabrication. Unfortunately, when inspecting at a late stage, it can be very difficult to isolate defects when the metal lines have been connected into complex networks. To by-pass this limitation, some inspections are conducted in laboratories on wafers in the early stage of the fabrication (metal
1
and
2
) by externally grounding certain metal lines. This approach, however, can only be done off-line and requires a skillful operator to achieve good results.
Other proposals for inspecting semiconductor wafers using charged particle beams are disclosed in copending patent application Ser. No. 08/782,740 (filed Jan. 13th, 1997), the contents of which are incorporated herein by reference, and in U.S. Pat. No. 5,578,821. U.S. Pat. No. 5,502,306 discloses the use of electron beams for inspecting masks. U.S. Pat. No. 5,578,821 describes the use of an electrode near to the surface of the substrate to establish a field-free region, the object being to avoid creating large potential differences between areas on the substrate.
Device critical dimensions are continuing to shrink and fabrication lines are increasingly adopting larger wafer sizes to cut average die manufacturing cost. This means that devices are more susceptible to contamination and processing imprecision and low yields are less tolerable due to high wafer cost and equipment capital. Increasingly, there is a demand for inspection techniques to detect defects and isolate the root cause at the earliest stage. However, no existing inspection tools or techniques are known which can detect defects in the fabrication of diffusion contacts and gate poly. These types of defects are not visible using optical microscopes or charged particle microscopes because they are hidden under the surface. Existing voltage contrast techniques are unable to find them because no difference in voltage contrast between the good and the bad open contacts; either bad or good contacts charge-up under the electron beam irradiation.
It is an object of the present invention to provide a technique which allows the detection of defects at an early stage of fabrication and overcome some or all of the limitations of the existing techniques.
SUMMARY OF THE INVENTION
The present invention provides a method of testing a semiconductor structure such as a finished or part-finished semiconductor wafer, a die on such a wafer, part of such a die, or even one functional element (e.g. a transistor or memory cell collectively known to those of ordinary skill in the art as active devices and which are comprised of interconnected structures such as poly gates, contacts and diffusions into the semiconductor wafer to form pn junctions.) of such a die. Those of ordinary skill in the art will recognize that each die on the wafer is an integrated circuit comprised of one or more active devices. The method comprises charging at least a part of the semiconductor structure; applying an electric field perpendicular to a surface of the structure while charging so as to determine charging potential and polarity (i.e. charging either positively or negatively); interrogating the structure including the chatted part with a charged particle beam, such as an electron beam, so as to obtain voltage contrast data for the structure; and analyzing the data to determine the functionality of the element.
Apparatus according to the invention for testing semiconductor structures, comprises: means for applying charge to at least part of the semiconductor structure, such as an electron beam, flood gun or mechanical probe; an electric field generator, typically an electrode spaced from the surface of the structure, which applies an electric field perpendicular to a surface of the structure so as to determine the potential and polarity of the charge applied to the element (i.e. positive or negative charge); a charged particle beam device such as an electron beam for interrogating the charged element; and a detector such as a secondary electron detector which obtains voltage contrast data from the structure on interrogation with the charged particle beam.
The present invention has the advantage that it provides for controlled positive and/or negative charging of the structure and so allows faults to be located which are either In invisible to previous techniques or would otherwise require Vss to be connected to be detected.
The preferred means for applying charge is an electron beam. This can be in the form of a relatively unfocussed flood gun if it desired to charge a large area of the structure, or focused beam where charging is to be in a specific area or of specific elements such as contact pads and the like. Other means for applying charge are focused ion beams and mechanical probes. It will be appreciated that where the term “electron beam” is used in this application, one or other of these alternatives might be used, depending on circumstances.
By providing for the application of an electric field perpendicular to the surface of the structure, it is possible to control the charging potential and polarity. The field can cause either more or less charged particles (electrons) to leave the surface than the number arriving from the charging means. In a particularly preferred embodiment, this is achieved using an electrode, which can be a grid or aperture plate according to requirem
Lo Chiwoei Wayne
Stoops Mariel
Talbot Christopher Graham
Applied Materials Inc.
Einschlag Michael B.
Sherry Michael
Tang Minh N
LandOfFree
Methods and apparatus for testing semiconductor and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for testing semiconductor and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for testing semiconductor and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3025720