Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2004-06-30
2008-08-12
Auve, Glenn A (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S243000, C710S317000, C370S362000, C370S412000
Reexamination Certificate
active
07412551
ABSTRACT:
Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.
REFERENCES:
patent: 6701407 (2004-03-01), Honjo et al.
patent: 7200699 (2007-04-01), Bose et al.
patent: 2003/0035375 (2003-02-01), Freeman
patent: 2004/0059862 (2004-03-01), Chan
patent: 2006/0031625 (2006-02-01), Chan
Bose Bijoy
Lakshmanamurthy Sridhar
Rosenbluth Mark B.
Vaz Irwin
Auve Glenn A
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
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