Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-10-27
2001-10-30
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S013000, C703S014000, C703S015000
Reexamination Certificate
active
06311309
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to software-controlled simulation of a circuit design. More specifically, the present invention provides a method for simulating a circuit design using a block diagram representation of the design in a graphical user interface.
Despite the great variety of software circuit design tools currently available, most circuit designers continue to generate their high level designs using pencil and paper. That is, the designer typically draws by hand in a notebook one or more high level block diagrams which may represent increasingly detailed levels of the circuit design. The current practice is to then take these block diagrams and manually convert them to one or more design files in some design file format, e.g., VHDL or Verilog. The circuit level implementations of the blocks in the block diagrams are then specified in these design files. Tedious manual conversions of this type are typically performed exclusively by one or more full time programmers.
There are computer aided drawing (CAD) tools with which a designer can create high level block diagrams in a graphical user interface. However, such CAD tools do not interface with the design tools used for defining the circuit level implementation of the individual blocks in the diagram. Even with an electronically created block diagram, unrelated design files must be created for the implementation of the individual blocks of the diagram. That is, a block diagram created with a currently available CAD tool is about as useful as a hand drawn block diagram with regard to the circuit level implementation of a design.
Once such design files are fully specified the functional operation of each may be individually simulated by a variety of well known techniques. That is, the operation of a design file written in VHDL may be simulated by the application of VHDL test vectors using a VHDL test bench. If, however, the designer wishes to simulate the operation of some combination of blocks in a high level diagram, an entirely new design file must be constructed which specifies all of the included blocks and their combined external interface. That is, there is currently no way in which the separate design files may be easily combined and simulated. The disadvantages of the current approach are manifest. With the addition of each new simulation design file, the file maintenance function associated with a particular design becomes increasingly complex. That is, the number of design files which must be updated when a change is made to one of the related files increases as the number of combination design files increases. And, as mentioned above with respect to the conversion of hand drawn block diagrams to design files, the creation of these simulation design files is highly labor intensive. Moreover, if related design files are not in the same format, as may be the case where a designer wishes to use a previously generated design file from a design entity library, they cannot be combined into a new design file for simulation until one of the files is completely specified in the same format as the other.
It is therefore desirable to provide a method by which different combinations of blocks in a block diagram may be easily combined and simulated together.
SUMMARY OF THE INVENTION
According to the present invention a method is provided by which a circuit designer may select a plurality of design files corresponding to blocks in a block diagram and simulate the combination of the selected blocks without having to create a separate design file. According to a specific embodiment, the designer creates a block diagram in a graphical user interface (GUI) and then generates individual design files representing the blocks in the diagram. The design files may be in any of a variety of graphic or text formats. Once the design files are sufficiently specified, the designer may select individual blocks in the GUI for simulation. A netlist is generated for the block using the information in the design file and a simulation is performed using the netlist. The designer may also select more than one block in the GUI for simulation of the combination of the selected blocks. A netlist is generated for the combination of blocks using the associated design files and an external interface for the combination of blocks is determined based on the design files and the interconnections between the various blocks as specified in the block diagram. A simulation is then performed using the combined netlist.
According to another specific embodiment, the designer generates a circuit design comprising a plurality of design files which may be in any of a variety of text formats. The circuit design is represented by a hierarchy tree in a text-mode user interface (TUI) which relates the design files associated with the circuit design. In the TUI, the designer selects one or more blocks for simulation in response to which a netlist is generated corresponding to the selected design file or files in much the same way as is done with the above-described embodiment. With either of the embodiments of the invention, the designer may perform as many simulations as desired using as many different combinations of blocks and/or design files as desired without having to create additional design files to facilitate the simulation.
Thus, the present invention provides a method for simulating a portion of a circuit design. The circuit design includes a plurality of design files each corresponding to one of a plurality of design entities in the circuit design. A subset of the design entities is selected. The subset of the design entities corresponds to the portion of the circuit design to be simulated. In response to selection of the subset of the design entities, a netlist is generated under software control directly from the design files associated with the subset of the design entities. The portion of the circuit design is then simulated using the netlist.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
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Altera Corporation
Beyer Weaver & Thom LLP
Siek Vuthe
Smith Matthew
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