Methods and apparatus for selective comment assertion

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C703S013000

Reexamination Certificate

active

07036107

ABSTRACT:
Methods and apparatus are provided for efficiently implementing a programmable chip using hardware description source files passed through multiple tools. A hardware description language source file is provided with mechanisms to allow tool-specific code to be handled by both a synthesis tool and by a simulation tool. Instructions are provided to direct a synthesis tool to read as code comments that a simulation tool is configured to disregard.

REFERENCES:
patent: 6519756 (2003-02-01), Kao et al.
patent: 6836877 (2004-12-01), Dupenloup
Van De Vanter, “Preserving the Documentary Structure of Source Code in Language-based Transformation Tools,” 2001 First IEEE Int'l Workshop on Source Code Analysis and Manipulation, pp. 131-141.
Some et al., “Parsing Minimization when Extracting Information from Code in the Presence of Conditional Compilation,” 1998 6th Int'l Workshop on Program Comprehension, pp. 118-125.
Bening et al., “Optimizing Multiple EDA Tools within the ASIC Design Flow,” IEEE Design & Test of Computers, pp. 46-55.
Exemplar Logic, Inc. “Leonardo Spectrum for Altera Reference Manual, Software Version v2001.1”, copyright 2001 Exemplar Logic, Inc. Jul. 2001.
Synplify, Inc., Synplify Reference Manual, Oct. 2001.

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