Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2005-01-11
2005-01-11
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000, C710S262000, C710S264000
Reexamination Certificate
active
06842811
ABSTRACT:
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debuts monitor mechanism.
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Barry Edwin Frank
Larsen Larry D.
Marchand Patrick R.
Pechanek Gerald G.
Mason Donna K.
Priest & Goldstein PLLC
PTS Corporation
Rinehart Mark H.
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