Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
Reexamination Certificate
2008-06-10
2008-06-10
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing sequence control
C712S244000, C712S248000
Reexamination Certificate
active
07386710
ABSTRACT:
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debug monitor mechanism.
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patent: 5384906 (1995-01-01), Horst
patent: 6405305 (2002-06-01), Meier et al.
Barry Edwin Franklin
Larsen Larry D.
Marchand Patrick R.
Pechanek Gerald George
Altera Corporation
Pan Daniel
Priest & Goldstein PLLC
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