Electrical computers and digital data processing systems: input/ – Interrupt processing – Multimode interrupt processing
Reexamination Certificate
1999-08-13
2002-05-07
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Interrupt processing
Multimode interrupt processing
C710S262000, C710S263000, C710S264000, C710S266000, C710S048000, C710S006000, C711S114000
Reexamination Certificate
active
06385683
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to RAID storage systems, and more particularly to RAID storage system controllers with improved performance.
The management of the multiple input/output (I/O) tasks which is inherent in processing RAID operations presents difficulties in providing the improved performance that is necessary for future generation RAID subsystems. This is due in part to the significant microprocessor overhead required to manage these large number of I/O tasks. In particular, a typical RAID read/modify/write command can require as many as six (6) or more individual I/O tasks. As one skilled in the art will appreciate, with the RAID controller designs currently known in the art, the controller's microprocessor typically must manage all these I/O tasks as they occur. The routines required to manage the RAID hardware set-up and the interrupt service threads for each of the individual RAID I/O tasks result in inefficient interruption of the microprocessor and thrashing of the microprocessor primary and secondary cache.
It is desirable, therefore, to reduce or offload at least a portion of the overhead from the primary microprocessor. It is further desirable to improve the management of multiple I/O tasks, particularly for RAID systems.
SUMMARY OF THE INVENTION
The present invention provides a storage system controller including a main processor, a memory coupled to the main processor, a device interface adapted to interface a peripheral component, such as a disk array, with the storage system controller, and an operations sequencer. The operations sequencer is adapted to receive an operation comprising a plurality of tasks from the main processor and to coordinate the execution of the plurality of tasks prior to interrupting the main processor. In this manner, the operations sequencer offloads at least some of the main processor overhead to improve processor efficiency.
One advantage of the present invention is the off-loading of overhead from the primary processor(s) by providing an operations sequencer that performs the hardware set-up and management tasks independent of the primary processor. The operations sequencer allows the primary processor to set-up the entire sequence of steps that will be executed for an I/O operation, such as a multi-step RAID operation. The primary processor then kicks off the sequencer with no further processing required by the processor until the sequencer has finished the operation or an exception has occurred that requires more sophisticated management than the sequencer has been designed to manage.
In one aspect, the main processor includes a RAID controller processor, the operations sequencer includes a RAID accelerator, and the peripheral component includes a RAID storage device. In this manner, the operations sequencer offloads a plurality of tasks for a RAID operation to improve controller efficiency.
In alternate aspects, the operations sequencer includes a co-processor in electrical communication with the main processor, or a co-processor disposed within the main processor. In further aspects, the operations sequencer includes a hardware state machine or an intelligent device interface.
In one aspect, the controller includes a plurality of device interfaces that are adapted to interface with a plurality of peripheral components. In this manner, the operations sequencer is adapted to coordinate operations for more than one peripheral component.
In still another aspect of the invention, the storage system controller further includes an interrupt management scoreboard coupled to or associated with the main processor or the operations sequencer. Exemplary scoreboards for use in the present invention are described in further detail in U.S. application Ser. No. 09/373,864, entitled “Methods and Apparatus for Using Interrupt Score Boarding with Intelligent Peripheral Devices,” filed contemporaneously herewith, the complete disclosure of which is incorporated herein by reference.
The present invention further provides exemplary methods of controlling a storage system. One particular method includes providing a storage system controller having a main processor, a memory, a device interface, and an operations sequencer, and providing a storage system in electrical communication with the device interface. The main processor sequences a first plurality of tasks to be executed to complete a desired operation, such as a RAID operation. The operations sequencer receives the first plurality of tasks from the main processor and coordinates an execution of the first plurality of tasks. The method includes issuing a primary interrupt to the main processor after all of the first plurality of tasks of the operation are executed. In one aspect, the main processor polls for completion of the plurality of tasks.
In one particular aspect, the storage system controller further includes an interrupt management scoreboard coupled to or associated with the main processor or the operations sequencer. In one aspect, the method includes the scoreboard receiving a task status for each of the first plurality of tasks that is executed. In one embodiment, the operations sequencer writes the test status to the scoreboard. In another embodiment, the main processor writes the task status to the scoreboard. The task status comprises an error notification or a task complete notification in one embodiment.
In one aspect, the method further includes issuing a secondary interrupt to the main processor if the execution of one of the first plurality of tasks results in an error. In one aspect, the device interface issues the secondary interrupt. In one particular aspect, the main processor initiates a retry of the error-producing task to the device interface in response to the secondary interrupt. In this manner, a task that produces an error can be addressed by the main processor without necessarily effecting the operations sequencer, which in one embodiment continues to coordinate the execution of other tasks.
Preferably, the sequencing step includes sequencing the first plurality of tasks into a desired execution sequence, and the coordinating step includes coordinating the execution of the first plurality of tasks in accordance with the desired execution sequence.
The operations sequencer preferably is capable of handling more than one operation. For example, in one aspect, the method further includes sequencing a second plurality of tasks to be executed to complete a second desired operation, coordinating a second execution of the second plurality of tasks, and issuing a second primary interrupt to the main processor. Preferably, the coordinating step coordinates the simultaneous execution of the first and second plurality of tasks. In one aspect, the desired operations include RAID operations.
In one aspect, the storage system controller further includes first and second interrupt management scoreboards (IMS). The first IMS receives a first task status for each of the first plurality of tasks executed, and the second IMS receives a second task status for each of the second plurality of tasks executed. In one aspect, a plurality of intelligent peripheral components and a plurality of device interfaces are provided.
In another method of the present invention, a method of controlling a storage system includes the steps of providing a storage system controller as previously described having an interrupt management scoreboard (IMS), and providing a device coupled with the device interface. The main processor sequences a group of N tasks to be executed to complete a desired operation, and the operations sequencer coordinates an execution of the group of N tasks. The method includes the IMS receiving a task status for each of the N tasks executed by the device. Upon completion of the N tasks, the IMS or the operations sequencer can interrupt the main processor notifying it that the N tasks are complete. Alternatively, the main processor can poll the IMS and/or the sequencer to determine when the N tasks have completed.
In one aspect,
DeKoning Rodney A.
Gates Dennis E.
Holt Keith W.
Kloeppner John R.
LSI Logic Corporation
Shin Christopher B.
Townsend & Townsend & Crew
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