Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2005-01-18
2008-09-23
Portka, Gary J (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C711S152000
Reexamination Certificate
active
07428619
ABSTRACT:
A synchronization scheme is provided for a multiprocessor system. In particular, a processor includes a buffer sync controller. The buffer sync controller is operative to allow or deny access by a subprocessor to shared data in a shared memory, such that a processor seeking to write data into or read data from the shared memory must ascertain certain shared parameter data processed by the buffer sync controller.
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Inoue Keisuke
Yasue Masahiro
Lerner David Littenberg Krumholz & Mentlik LLP
Portka Gary J
Sony Computer Entertainment Inc.
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