Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-12-04
2003-09-23
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
06624056
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to improvements to integrated circuit layout and design. More particularly, the present invention addresses methods and apparatus for parallel line layouts having reduced capacitive power dissipation.
BACKGROUND OF THE INVENTION
As process technology advances, metal lines utilized to connect components on semiconductor chips are getting narrower and narrower. The spacing between such lines is getting smaller, and in order to minimize the impact on line resistance, these metal lines are being made taller. As a result, a dominant component of capacitance of such a line is the coupling capacitance between adjacent lines on the same metallization layer.
Commercially available place and route design tools give users the ability to specify wider spacing rules for specific materials, connections and the like. For example, it is common practice to use this approach to minimize delay and power loss associated with specific networks of connections such as clock networks in a design.
Further, in the literature, a technique has been instrumented which is sometimes referred to as “power driven placement”. In this approach, signals with a high level of switching activity are identified through dynamic simulation of the design. By placing the devices and receivers associated with these signals closer together during cell placement, the net capacitance is reduced and so is the power. This technique is built upon timing-driven placement algorithms which place cells closer together if it helps the design to achieve its timing constraints.
SUMMARY OF THE INVENTION
Among its several aspects, the present invention addresses the reduction of the coupling capacitance between conductors on the same metallization layer. Modern integrated circuits are often built using at least five or six layers of metallization. Most circuits including custom circuits and standard-cell based circuits can achieve fairly good densities using only three layers of metal. The fourth, fifth and sixth layers of metal are often used for power distribution, clock distribution and inter-module routing for system-on-a-chip designs. In general terms, the present invention provides methods and apparatus for systematically increasing spacing between conductors on a given metal layer from one or more metal pitches to a greater number of metal pitches by using higher layers of metal to route signals in the spaces between alternating conductors on the underlying metal layer. Metal pitches used in placed and routed designs are most frequently based on, but not limited to, line-to-via spacing and via-to-via spacing. As addressed further below, the present techniques can be applied to, but are not limited to, both standard cell designs and custom designs. They are particularly applicable for 0.25 micron (&mgr;m) chip design processes and below.
These and other advantages and aspects of the present invention will be apparent from the drawings and the Detailed Description which follows below.
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Brown David Lyndell
Chandna Ajay
O'Brien Tom
Le Vu A.
Luhrs Michael K.
Priest & Goldstein PLLC
PTS Corporation
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