Methods and apparatus for providing bit-reversal and...

Details Methods and apparatus for providing bit-reversal and... Methods and apparatus for providing bit-reversal and...

2011-05-23

2011-12-20

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S027000, C712S010000, C712S011000, C712S014000, C712S035000, C712S300000, C711S202000

Reexamination Certificate

active

08082372

ABSTRACT:
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

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Weste et al., Principles of CMOS VLSI Design, Addison Wesley, 1985, pp. 9-10 and 174-175.

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