Methods and apparatus for processing video data

Details Methods and apparatus for processing video data Methods and apparatus for processing video data

1996-08-19

2001-02-20

Rao, Andy (Department: 2713)

Pulse or digital communications

Bandwidth reduction or expansion

C348S403100, C348S405100

Reexamination Certificate

active

06192073

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to data processing by computers, and more particularly to processing of video data by computers.
Computers have been used to compress and decompress system data. System data include video data which include images of still and/or moving pictures. System data may also include audio data, for example, a sound track of a motion picture. It is desirable to provide methods and circuits that allow fast and memory efficient processing of video data.
SUMMARY
The present invention provides methods and circuits that allow fast and memory efficient processing of video data. In some embodiments, a computer system of the present invention includes three processors capable to operate concurrently—a scalar processor, a vector processor and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data (SIMD) processor. Such operations include: 1) a linear data transform such as a discrete cosine transform (DCT); and 2) motion compensation. The bitstream processor performs operations that include operations on particular bits rather than on words or half-words. Such operations include Huffman and RLC encoding or decoding used, for example, with MPEG-1, MPEG-2, H.261, and H.263 standards. The scalar processor performs high level video processing (for example, picture level processing), synchronizes operation of the vector and bitstream processors, and controls interface with external devices.
In some embodiments, the computer system can process several data streams concurrently. As a result, the user of the computer system can have a video conference with two or more parties. Multiple data streams can be processed concurrently because the bitstream processor can switch contexts to encode or decode different data streams concurrently in real time.
In some embodiments, the scalar and vector processors are programmable in the sense that each of the two processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor is not programmable in the sense that the bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction. Rather, the bitstream processor can be programmed to perform a whole video data processing operation on a set of video data. Making the bitstream processor not capable of being programmed to execute a single arithmetic or Boolean instruction allows the bitstream processor to be faster. Programmability of the scalar and vector processors facilitates adapting the system to changes in video data encoding and decoding standards.
In some embodiments, the system can handle different video data standards. For example, in some embodiments, the system can handle all of MPEG-1, MPEG-2, H.261, and H.263. To reduce the size of memory used for Huffman encoding and decoding tables, the tables are coded to share memory. Appropriate logic is supplied to derive correct Huffman codes from the coded tables stored in the shared memory.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.


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