Methods and apparatus for power control in a scalable array...

Details Methods and apparatus for power control in a scalable array... Methods and apparatus for power control in a scalable array...

2005-11-15

2005-11-15

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Reconfiguration

C713S001000, C713S002000

Reexamination Certificate

active

06965991

ABSTRACT:
A reconfigurable register file system is described. The reconfigurable register file system includes an instruction register for storing an instruction specifying an operational requirement, a reconfigurable register file comprising an odd register file having at least one data read port, and an even register file having at least one data read port. The reconfigurable register file system may further suitably include an execution unit connected to the data read ports of the odd and even register files and port usage control logic connected to the instruction register and the reconfigurable register file to control the odd register file and the even register file port address input so that data read port lines change only as needed to support the operational requirement specified by the instruction. The port usage control logic may further include a gating circuit connected to the reconfigurable register files and a clock input, the gating circuit being operable for gating the clock off so no change of state of the reconfigurable register files occurs for each cycle when change is not necessary and gating the clock on so new data is clocked into the reconfigurable register files for each cycle when change is desired.

REFERENCES:
patent: 4484324 (1984-11-01), Orsic
patent: 5613151 (1997-03-01), Dockser
patent: 6134648 (2000-10-01), Peterson et al.

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