Methods and apparatus for power control in a scalable array...

Details Methods and apparatus for power control in a scalable array... Methods and apparatus for power control in a scalable array...

2005-01-18

2005-01-18

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Reconfiguration

C713S320000, C710S018000, C710S261000, C710S266000

Reexamination Certificate

active

06845445

ABSTRACT:
Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.

REFERENCES:
patent: 5495617 (1996-02-01), Yamada
patent: 5628020 (1997-05-01), O'Brien
patent: 6609193 (2003-08-01), Douglas et al.
patent: 6625740 (2003-09-01), Datar et al.

Affiliated with

Also associated with

Rating

Methods and apparatus for power control in a scalable array... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatus for power control in a scalable array..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for power control in a scalable array... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3434454