Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2005-06-28
2005-06-28
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S021000, C712S010000, C712S011000, C711S140000, C345S506000
Reexamination Certificate
active
06912608
ABSTRACT:
Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.
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Baker David
Barry Edwin Franklin
Cope Bryan Garnett
Wolff Edward A.
Mason Donna K.
Priest & Goldstein
PTS Corporation
Rinehart Mark H.
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