Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-04
2002-08-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06430731
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to signal timing analysis techniques and, more particularly, to methods and apparatus for performing slew dependent signal bounding for use in signal timing analysis.
BACKGROUND OF THE INVENTION
The propagation of rise and fall times, i.e., slews, has been a long standing problem in static timing analysis, e.g., see J. K. Ousterhout, “A Switch-Level Timing Verifier for Digital MOS VLSI,” in IEEE Trans. on CAD, vol. 3, July 1985, pp. 336-349, and N. Hedenstierna and K. O. Jeppson, “CMOS Circuit Speed and Buffer Optimization,” IEEE Trans. on CAD, vol. 6, March 1987, pp. 270-281. Signals arriving at a given node of a circuit may be generated from different input patterns and may travel through different paths. In a static timing analysis, all of these signals are compared. One signal, namely, the latest signal, is selected to represent the worst-case arrival time bound, and kept to carry through the circuit network (a similar approach can be used for the earliest arriving or early-mode signal). The validity of this approach is based on the observation that the latest signals always yield the latest arrival times when they propagate to the primary output. The monotone nature of signal propagation time in this plain form is true, only if the slew variations among the signals are small.
Examples of conventional timing analysis approaches which rely on this observation include: R. B. Hitchcock, Sr., “Timing Verification and the Timing Analysis Program,” 19
th
Design Automation Conference. June 1982, pp. 594-604; K. A. Sakallah, T. N. Mudge and O. A. Olukotun, “Check Tc and Min Tc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits,” in Proc. ICCAD, November 1990, pp.552-555; G. Szymanski and N. Shenoy, “Verify Clock Schedule,” in Proc. ICCAD, November 1992, pp. 124-131; and J. F. Lee, D. T. Tang, and C. K. Wong, “Algorithm for Circuits with Level-Sensitive Latches,” in IEEE Trans. on CAD, vol. 15, May 1996, pp.535-543.
However, in reality, circuit designers encounter signals with a wide range of slews. The delay through a CMOS gate depends on the signal slew present at its inputs. The typical approach to accommodate the slew is via the following heuristic method known as the “latest arriving method.” The latest arriving method dictates that during propagation through each gate, always adopt the slew carried by the latest arriving signal. There are two potential pitfalls with this latest arriving method.
First, the worst-case arrival time bound calculated may be invalid when the latest arriving method is employed, since an earlier signal with a slow slew may eventually reach the primary output later. For example in
FIG. 1
, assume that the arrival time (a
ƒ
) of the fast signal at the output of gate
1
is later than that (a
S
) of the slow signal. Let the delay through gate
2
be d
ƒ
and d
s
respectively for the fast and slow signals. Since d
ƒ
<d
S
, the situation a
ƒ
+d
ƒ
<a
S
+d
S
may be reached. This means that the slow signal becomes the latest one at the output of gate
2
, and therefore can not be ignored.
Second, the monotonic property of signal propagation may be violated when the latest arriving method is employed, so that the convergence of the worst-case timing bound is no longer guaranteed. Let us assume that in
FIG. 1
, the fast signal is only slightly later than the slow signal at the output of gate
1
. So the fast signal is chosen to propagate through gate
2
, and the worst-case arrival time calculated at the output of gate
2
is a
ƒ
+d
ƒ
. If the fast signal is sped up so that its arrival time at the output of gate
1
is a
ƒ
<a
S
, then the slow signal is chosen to propagate, and the worst-case time at the output of gate
2
becomes a
S
+d
S
which is greater than a
ƒ
+d
ƒ
. The monotonic property is thus violated.
Therefore, it would be desirable to have methods and apparatus which provide improved ways to define the worst-case signals for timing analysis purposes so as to, among other things, avoid the problems associated with the above-described conventional latest arriving method.
SUMMARY OF THE INVENTION
The present invention provides methods and apparatus which provide improved ways to define the worstcase signals for timing analysis purposes so as to, among other things, avoid the problems associated with the above-described conventional latest arriving method.
In one aspect of the invention, a method for use in signal timing analysis with respect to a circuit having at least one gate includes the step of determining a first constraint slew sensitivity value and a second constraint slew sensitivity value for the gate according to a specified bounding technique. Then, a representative signal for the gate is computed in accordance with the first and second values including an arrival time and slew rate, wherein the representative signal bounds signal paths by bounding a maximum slew. sensitivity path and a minimum slew sensitivity path. Such a representative signal may be computed for a worst case late-mode analysis and/or a best case early-mode analysis.
The bounding technique may be selected by a user at the time the user inputs the schematic of the circuit on which timing analysis is to be performed. The invention provides for the use of bounding techniques such as, for example, maximum slew, minimum slew, half envelope, full envelope, modified half envelope, modified max slew, modified min slew, least upper bound, and greatest lower bound. The invention may be employed in accordance with static timing analysis associated with VLSI circuit design, however, one of ordinary skill in the art will appreciate various other applications such as, for example, circuit tuning given the inventive teachings herein. The invention may also be implemented in the form of a static timer apparatus.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5508937 (1996-04-01), Abato et al.
patent: 5535145 (1996-07-01), Hathaway
patent: 5651012 (1997-07-01), Jones et al.
patent: 6145117 (2000-11-01), Eng
patent: 6301693 (2001-10-01), Naylor et al.
Venkatesh et al, “Timing Abstraction of Intellectual Property Blocks,” IEEE, May 1997, pp. 99-102.*
Kayssi et al, “Analytical Transitient Response of CMOS Inverters,” IEEE, Jan. 1992, pp. 42-45.*
Xiao et al, “Worst Delay Estimation in Crosstalk Aware Static Timing Analysis,” IEEE, Sep. 2000, pp. 115-120.*
R.B. Hitchcock, Sr. et al., “Timing Analysis of Computer Hardware,” IBM J. Res. Develop., vol. 26, No. 1, pp. 100-105, Jan. 1982.
J.K. Ousterhout, “A Switch-Level Timing Verifier for Digital MOS VLSI,” IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 3, pp. 336-348, Jul. 1985.
N. Hedenstierna et al., “CMOS Circuit Speed and Buffer Optimization,” IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 2, pp. 270-281, Mar. 1987.
K.A. Sakallah, et al., “checkTcand minTc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits,” Proc. ICCAD, pp. 552-555, Nov. 1990.
T.G. Szymanski et al., “Verifying Clock Schedules,” Proc. ICCAD, pp. 124-131, Nov. 1992.
J-F Lee et al., “A Timing Analysis Algorithm for Circuits with Level-Sensitive Latches,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15., No. 5, pp. 535-543, May 1996.
Lee Jin-Fuw
Ostapko Daniel Lawrence
Soreff Jeffrey Paul
Wong Chak-Kuen
Otterstedt Paul J.
Ryan & Mason & Lewis, LLP
Siek Vuthe
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