Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2008-07-01
2008-07-01
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C370S394000, C710S065000, C710S068000, C710S072000
Reexamination Certificate
active
07395363
ABSTRACT:
Symbols are prepared for transmission by representing each bit of the symbols by a cluster of consecutive bits, identical to the bit, in a transmission bit sequence. The transmission bit sequence is transmitted at a particular bit rate. A reception bit sequence of received bits is received at the particular bit rate, and the reception bit sequence is identical to the transmission bit sequence in the absence of errors. The symbols are reconstructed from the reception bit sequence of received bits by identifying boundaries of clusters of received bits in the reception bit sequence and selecting an inner bit of each of the clusters of received bits as a bit of a reconstructed symbol. The boundary identification involves comparing neighboring received bits. The transmission of the transmission bit sequence and reception of the reception bit sequence may conform to the Peripheral Components Interconnect (PCI) Express Specifications.
REFERENCES:
patent: 6184714 (2001-02-01), Kirsch et al.
patent: 6275067 (2001-08-01), Kirsch et al.
patent: 6300795 (2001-10-01), Kirsch et al.
patent: 6320417 (2001-11-01), Kirsch et al.
patent: 6421357 (2002-07-01), Hall
patent: 6690757 (2004-02-01), Bunton et al.
patent: 6963532 (2005-11-01), Dent
patent: 2002/0110203 (2002-08-01), Sarkar
patent: 2003/0128767 (2003-07-01), Kudoh
patent: 2002204280 (2002-07-01), None
patent: 00377412 (1999-12-01), None
patent: 00436704 (2001-05-01), None
patent: 00501018 (2002-09-01), None
patent: WO 0161954 (2001-08-01), None
Budruk, Ravi; Anderson, Don; and Shanley, Tom; PCI Express System Architecture; MindShare, Inc., copyright 2004, pp. 93,400-401, and 419-421.
U.S. Appl. No. 10/629,967, filed Jul. 30, 2003, Kwa et al.
R. Tielert: “High Speed I/O Circuits (suited for advanced sub-μm CMOS Technologies)” 2003, TU Kaiserslautem, XP 002360106: Retrieved from the internet: URL:http://mikro.ee.tu-berlin.de/ifm/AW/HandOuts /tielert.pdf> retrieved on Dec. 20, 2005.
Brewer, Sekel: “PCI Express Technology” Feb. 2004, Dell, XP002360058. Retrieved from the internet: URL:http://www.dell.com/downloads/global/vectors/2004—pciexpress.pdf> retrieved on Dec. 19, 2005.
International Search Report for Application No. PCT/US2005/031560 mailed Jan. 5, 2006.
Taiwanese Search Report for Application No. 94130717 received on Nov. 2, 2007.
Auve Glenn A.
Intel Corporation
Pearl Cohen Zedek Latzer LLP
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