Methods and apparatus for memory map generation on a...

Details Methods and apparatus for memory map generation on a... Methods and apparatus for memory map generation on a...

2006-03-07

2006-03-07

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

Reexamination Certificate

active

07010666

ABSTRACT:
Methods and apparatus are provided for the automatic assignment of addresses for slave components to be implemented on a programmable chip. Slave components including peripheral components and peripheral interfaces are assigned to master components. In some examples, master components and slave components are analyzed using criteria such as address space availability and address span width to more efficiently assign base addresses for the various slave components on a programmable chip.

REFERENCES:
patent: 5218684 (1993-06-01), Hayes et al.
patent: 6075935 (2000-06-01), Ussery et al.
patent: 2002/0059054 (2002-05-01), Bade et al.
patent: 0 949 777 (1999-04-01), None
patent: WO 01/05083 (2001-01-01), None
PCT International Search Report in International Application No. PCT/US2004/007660, dated Oct. 1, 2004, 11 pages.

Affiliated with

Also associated with

Rating

Methods and apparatus for memory map generation on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatus for memory map generation on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for memory map generation on a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3551565