Methods and apparatus for making placement sensitive logic...

Details Methods and apparatus for making placement sensitive logic... Methods and apparatus for making placement sensitive logic...

2006-10-18

2009-10-27

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07610568

ABSTRACT:
Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change. The already placed chip design is pruned to create a set of valid flops and valid scan chains based on a set of pruning rules. A unified flop database is generated containing physical location and connection information for the new flops and the set of valid flops. A change file for the new flops, selected valid flops, and valid scan chains associated with the selected valid flops is generated meeting allocation and placement sensitive signal connection rules. The new flops are connected to the selected valid flops allowing design for test requirements to be met.

REFERENCES:
patent: 7127695 (2006-10-01), Huang et al.
patent: 2006/0271899 (2006-11-01), Tan et al.
patent: 2006/0282810 (2006-12-01), Dutt et al.

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