Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1994-06-30
1998-04-21
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395874, 395728, 395873, 395859, 395860, 711118, 711 3, G06F 1316
Patent
active
057428310
ABSTRACT:
Methods and apparatus for maintaining cache coherency for pending load operations. A processor is selectively stalling only when there exists certain relationships between the address of an incoming store instruction and the addresses of the pending load instructions. The address specified by an incoming store instruction is compared with all the addresses specified by the pending load instructions that are stored in a bus queue. The processor is stalled from issuing subsequent instructions and executing the store instruction if the comparison results in a match of the store instruction address with any of the addresses of the pending load instructions. Instruction issue and execution of the store instruction are unstalled when data from the matching load instruction address returns. Alternatively, a count of the number of load instructions pending in the bus queue for each specified address may be maintained. Upon receiving a store instruction, a stall occurs if the count for a corresponding address specified by the store instruction is non-zero. The count for an address specified by a load instruction is incremented if the load instruction misses the cache. When the requested data returns from external memory, the count for the address specified by the missed load instruction is decremented. When data from the load instruction address that matches the store instruction address returns and the count for the address specified by the stalled store instruction is zero, then instruction issue and execution of the store instruction are unstalled.
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Intel Corporation
Peikari J.
Swann Tod R.
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