Methods and apparatus for low power SRAM using evaluation...

Details Methods and apparatus for low power SRAM using evaluation... Methods and apparatus for low power SRAM using evaluation...

2006-11-15

2008-09-09

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S203000, C365S189011

Reexamination Certificate

active

07423900

ABSTRACT:
Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.

REFERENCES:
patent: 2004/0130926 (2004-07-01), Nakase
patent: 2006/0291300 (2006-12-01), Di Gregorio
patent: 2007/0019461 (2007-01-01), Adams et al.
patent: 2007/0041239 (2007-02-01), Takeda

Affiliated with

Also associated with

Rating

Methods and apparatus for low power SRAM using evaluation... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatus for low power SRAM using evaluation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for low power SRAM using evaluation... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3985872