Electrical computers and digital processing systems: processing – Instruction alignment
Reexamination Certificate
2006-11-07
2006-11-07
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction alignment
Reexamination Certificate
active
07134000
ABSTRACT:
An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer. The alignment control logic includes predecoders for predecoding the instructions to provide instruction length information and pointer generation logic responsive to the instruction length information for generating a current instruction pointer for controlling transfer of instructions to the aligned instruction buffer.
REFERENCES:
patent: 5463748 (1995-10-01), Schwendinger
patent: 5668984 (1997-09-01), Taborn et al.
patent: 5721855 (1998-02-01), Hinton et al.
patent: 5832249 (1998-11-01), Tran et al.
patent: 5835967 (1998-11-01), McMahan
patent: 5845099 (1998-12-01), Krishnamurthy et al.
patent: 5896543 (1999-04-01), Garde
patent: 5930508 (1999-07-01), Faraboschi et al.
patent: 5978899 (1999-11-01), Ginosar et al.
patent: 6061779 (2000-05-01), Garde
patent: 6141742 (2000-10-01), Favor
patent: 6314509 (2001-11-01), Tremblay et al.
patent: 6453278 (2002-09-01), Favor et al.
patent: 6694425 (2004-02-01), Eickemeyer
Preliminary Examination Report from a corresponding Taiwan Patent Application No. 93114616 dated May 25, 2006.
Duraiswamy Deepa
Kannan Srikanth
Singh Ravi Pratap
Tran Thang M.
Analog Devices Inc.
Chan Eddie
Johnson Brian
Wolf Greenfield & Sacks P.C.
LandOfFree
Methods and apparatus for instruction alignment including... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for instruction alignment including..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for instruction alignment including... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3660144