Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2000-03-21
2001-07-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C365S189030
Reexamination Certificate
active
06259648
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to computer circuitry and, more particularly, to a method and apparatus for implementing a “pseudo” dual port memory from a single port zero bus turnaround random access memory (RAM).
Dual port memories are useful for numerous applications and are particularly well suited for communications and multiprocessor systems. For example, communications applications known as Asynchronous Transfer Mode (ATM) require large amounts of data to be transferred between two processing devices which is easily accomplished using dual port memories. And, in multiprocessor systems, dual port memories enable one processor to write data into an array while another processor can read data out of the array.
One specialized form of dual port memory is a dual port first-in first-out (FIFO) circuit. As its name implies, information is written into a FIFO circuit in sequence and read out of the circuit in the same sequence after some delay. A FIFO circuit has one port through which data is written and one port through which data is read.
Dual port random access memories (RAMs) are constructed using a variety of techniques. In a first conventional technique, each memory cell is truly dual port and thus requires eight transistors. Because eight transistor dual port memory cells make the memory array itself quite large, integrated circuit memories based on this technique are expensive. A second technique utilizes standard single port static RAM cells with a partitioned array. If both ports simultaneously attempt to access the same partition, then one of the accesses must be delayed. As the number of partitions increases, the likelihood that a collision will occur decreases, but the cost increases due to the extra decoding and collision detection circuitry. A third technique accesses a single port RAM at twice the speed of an external clock signal such that one port is accessed during a first portion of the clock cycle and the other port is accessed during the second portion of the clock cycle.
While such known techniques provide dual port memories, some utilizing single port memories for their construction, there is a continuing need to advance the art by providing alternate methods and apparatus for producing dual port memories. Preferably, such dual port memories would utilize single port RAMs yet provide dual port memories that are inexpensive and also fast.
SUMMARY OF THE INVENTION
The methods and apparatus of the present invention currently meet this need by providing a pseudo dual port memory using a zero bus turnaround random access memory (RAM) wherein data words stored in the RAM each comprise a plurality of data words for the pseudo dual port memory. Thus, words written to the dual port memory are accumulated to assembly a single RAM word which is written into an addressed location within the RAM. And, words read from the RAM also make up a plurality of data words for the dual port memory and are stored and multiplexed out as individual words. In the illustrated embodiment, each RAM word comprises two dual port memory words; however, other multiples, preferably powers of 2, can be used in the present invention such that each RAM word can comprise, 4, 8, 16, etc. dual port memory words.
In accordance with one aspect of the present invention, a pseudo dual port memory comprises a single port zero bus turnaround random access memory (RAM) storing M bit data words. At least one data input register provides at least two subgroups with each of the subgroups having M/2 data input storage locations and M data input storage locations of the at least one data input register are coupled to M data input leads of the RAM. At least one data output register provides two subgroups with each of the subgroups having M/2 data output storage locations and M data output storage locations of the at least one data output register are coupled to M data output leads of the RAM. Memory addressing circuitry is coupled to address leads of the RAM. Control circuitry is coupled to the RAM, the at least one data input register and the at least one data output register. The control circuitry performs a data write by setting a write address within the memory addressing circuitry and writing a first data word having M/2 bits into a first one of the at least two subgroups of the at least one data input register on a first clock pulse, writing a second data word having M/2 bits into a second one of the at least two subgroups of the at least one data input register on a second clock pulse, and on a third clock pulse, writing data from the first and second ones of the at least two subgroups of the at least one data input register into a storage location in the RAM corresponding to the write address.
The control circuitry further may interleave data reads with data writes by setting a read address within the memory addressing circuitry simultaneously with the writing of the second one of the at least two subgroups of the at least one data input register, and reading a data word having M bits from a location corresponding to the read address into the two subgroups of the at least one data output register on a fourth clock pulse. In a currently preferred embodiment, the pseudo dual port memory performs a FIFO operation. For the FIFO application, the memory addressing circuitry comprises a write counter and a read counter. For each write operation of the RAM for the FIFO, the control circuitry increments the write counter, and for each read operation of the RAM for the FIFO, the control circuitry increments the read counter. For the FIFO application, the pseudo dual port memory may further comprise a word counter which is incremented by 2 for each write operation of the RAM for the FIFO and decremented by 2 for each read operation of the RAM for the FIFO. The at least one data input register may comprise at least two data input registers, each having M/2 data input storage locations. In a currently preferred embodiment, the at least one data input register comprises first, second and third data input registers each having M/2 data input storage locations with the first and second data input registers or the second and third data input registers being selectively coupled to M data input leads of the RAM. The at least one data output register may comprise first and second data output registers each having M/2 data output storage locations, the first and second data output registers being coupled to M data output leads of the RAM.
In accordance with another aspect of the present invention, a pseudo dual port memory comprises a single port zero bus turnaround random access memory (RAM) storing M bit data words. At least one data input register is provided and has at least M data input storage locations and provides X subgroups each having M/X data input storage locations where X is a power of 2. M of the at least M data input storage locations of the at least one data input register are coupled to M data input leads of the RAM. At least one data output register is provided and has M data output storage locations and provides X subgroups each having M/X of the data storage locations. The data output register is coupled to M data output leads of the RAM. Memory addressing circuitry is coupled to address leads of the RAM. Control circuitry is coupled to the RAM, the at least one data input register and the at least one data output register. The control circuitry performs a data write by writing a first data word having M/X bits into a first one of the X subgroups of the at least M data storage locations of the at least one data input register on a first clock pulse, writing second through X data words each having M/X bits into second through X ones of the X subgroups of the at least M data storage locations of the at least one data input register on second through X clock pulses, setting a write address within the memory addressing circuitry on an X−1 clock pulse and writing data written into the first through X subgroups of the at least M data storage locations of the a
King and Schickli PLLC
Nelms David
Systran Corporation
Tran M.
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