Methods and apparatus for implementing high speed data communica

Details Methods and apparatus for implementing high speed data communica Methods and apparatus for implementing high speed data communica

1996-05-13

1999-07-13

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

G06F 1314

Patent

active

059220619

ABSTRACT:
A self-timed high speed data communications system includes an N-bit wide data path and a three-bit wide event path. Six states of the event path are used to indicate when data is on the data path for reading and when the data path is available for transmission of data. In a presently preferred embodiment, the event path has three stable states and three meta-stable states. The initial state of the event path is a first stable state. When a user places data on the data path, the event path assumes a first meta-stable state. After the data is read by all users, the event path assumes a second stable state. Further transmission and reception of data cycles the event path through alternating meta-stable and stable states. The event path is preferably zero dominant (one recessive) and stable states are indicated when only one of the three bits are asserted by all users. Meta-stable states are indicated when a transmitting user asserts one bit of the event path and at least one other users asserts another bit of the event path. Acknowledgement of data reception by each user is signalled by the user de-asserting a bit of the event path. Both wired and wireless communications systems are disclosed. Several wireless signalling systems include coherent and non-coherent systems, FSK systems and pulse keyed systems. Apparatus for the wired and wireless systems are also disclosed. Efficient software implementation of the invention is also disclosed.

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