Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2003-10-07
2010-02-02
Cleary, Thomas J (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S305000, C327S144000
Reexamination Certificate
active
07657689
ABSTRACT:
Methods and apparatus are provided for handling reset events in a bus bridge. A system on a programmable chip includes master components and slave components supporting various bus protocols. Bus bridges allow components using different bus protocols to interact. Reset of a distinct subset of programmable chip components or the synchronization of reset signals across disparate clock domains is allowed by effectively handling reset related signals at a bus bridge.
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Crosland Andrew
Draper Andrew
Altera Corporation
Cleary Thomas J
Weaver Austin Villeneuve & Sampson LLP
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